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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bekiaris, D. Xydis, S. Economakos, G. Pekmestzi, K. |
| Copyright Year | 2009 |
| Description | Author affiliation: Department of Electrical and Computer Engineering, National Technical University of Athens, Iroon Polytechneiou 9, 157 80, Zografou, Greece (Bekiaris, D.; Xydis, S.; Economakos, G.; Pekmestzi, K.) |
| Abstract | This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-Vth CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-Vth Multiplication-Addition units by their high-Vth counterparts, taking into account the timing slack of each unit and the word-level binary representation of the units' coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69–25.85% for several clock period constraints, compared to the low-Vth FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation. |
| Starting Page | 415 |
| Ending Page | 418 |
| File Size | 317533 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424450909 |
| DOI | 10.1109/ICECS.2009.5410902 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-13 |
| Publisher Place | Tunisia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Design methodology Finite impulse response filter CMOS technology Equations Sleep Threshold voltage Subthreshold current Tunneling Electronic mail Libraries |
| Content Type | Text |
| Resource Type | Article |
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