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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ben-Hamida, N. Sitch, J. Flemke, P. Pollex, D. Schvan, P. Greshishchev, Y. Shing-Chi Wang Falt, C. |
| Copyright Year | 2009 |
| Description | Author affiliation: Metro Ethernet Network, Nortel, Ottawa, Canada (Ben-Hamida, N.; Sitch, J.; Flemke, P.; Pollex, D.; Schvan, P.; Greshishchev, Y.; Shing-Chi Wang; Falt, C.) |
| Abstract | A clock recovery circuit for a 40Gb/s optical coherent receiver realized in CMOS 90nm technology is presented. The core PLL generates less 0.3ps rms jitter for a bandwidth of 0.5MHz. This is mainly due to the on-chip differential LC VCO with power supply regulation. The VCO operates at 11.5GHz center frequency with a 25% tuning range. Its phase noise at 1MHz offset is better than −110dBc/Hz, and consumes 3mW of power. In tone acquisition mode the PLL is a regular charge pump PLL, while in data acquisition mode the DSP core corrects the frequency through the tuning ports. The presented PLL is one of the key components in the 24Gs/s ADC and coherent receiver chip. |
| Starting Page | 695 |
| Ending Page | 698 |
| File Size | 625808 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424450909 |
| DOI | 10.1109/ICECS.2009.5410782 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-13 |
| Publisher Place | Tunisia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Clocks Quadrature phase shift keying Optical receivers Phase locked loops CMOS technology Voltage-controlled oscillators Frequency Tuning Circuits Optical pumping |
| Content Type | Text |
| Resource Type | Article |
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