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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shengyang Wang Jiafeng Zhu Zhihua Qu Jianhui Wu |
| Copyright Year | 2009 |
| Description | Author affiliation: National ASIC Research Center Southeast University, Nanjing China 210096 (Shengyang Wang; Jiafeng Zhu; Zhihua Qu; Jianhui Wu) |
| Abstract | A novel half-integer multi-modulus programmable divider was presented in this paper. It is based on the combination of the zipper divider structure and the reversed phase-switching technique (RPST). To solve the unwanted division ratio (DR) decreasing problem which is inevitably introduced by RPST, we can set DR one more than the expected value with smart design of the feedback control block. Also, we adopt a power saving method to reduce the divider's power consumption about 21% on average. The proposed divider can be used in fractional-N frequency synthesizers to suppress the quantization noise with the folded DR step size. |
| Starting Page | 739 |
| Ending Page | 742 |
| File Size | 290726 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424450909 |
| DOI | 10.1109/ICECS.2009.5410797 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-13 |
| Publisher Place | Tunisia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Frequency conversion Frequency synthesizers Feedback control Energy consumption Quantization 1f noise Application specific integrated circuits Delta modulation Digital modulation Frequency modulation |
| Content Type | Text |
| Resource Type | Article |
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