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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Raikos, G. Vlassis, S. |
| Copyright Year | 2009 |
| Description | Author affiliation: Electronics Laboratory, Physics Department, University of Patras, Rio Patras, Greece (Raikos, G.; Vlassis, S.) |
| Abstract | A voltage squarer based on bulk-driven PMOS transistors is proposed in this paper. Circuit topology employs a voltage attenuator and the quadratic ID/VG characteristic of a MOS in saturation. The squarer was designed with a 0.8V supply voltage using standard 0.35um CMOS process, which offers large value of threshold voltage. The squarer topology was modified for 0.18um CMOS process, which threshold voltage was smaller, operating under the extreme low supply voltage of 0.5V. The output current is proportional to square of the input voltage in each case. Simulation results verify the theoretical analysis demonstrating small relative error and fast transient response. |
| Starting Page | 159 |
| Ending Page | 162 |
| File Size | 318759 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424450909 |
| DOI | 10.1109/ICECS.2009.5410960 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-13 |
| Publisher Place | Tunisia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Threshold voltage CMOS process MOSFETs Attenuators Circuit topology MOS devices Laboratories Physics Low voltage Signal processing |
| Content Type | Text |
| Resource Type | Article |
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