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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ezawa, H. Miyata, M. Inoue, H. |
| Copyright Year | 1997 |
| Description | Author affiliation: Integrated Circuit Adv. Process Eng. Dept., Toshiba Corp., Yokohama, Japan (Ezawa, H.) |
| Abstract | A novel eutectic solder bump process, which allows ULSI chips area array pad layout, has been developed. Straight side wall bumps as plated using a new negative-type photoresist and eutectic solder electroplating provide several advantages over conventional mushroom bumps. The novel developed process gives the bump height uniformity as reflowed of less than 10% within the wafer. Composition measurements using ICP spectrometry have been performed to investigate the bump height dependence on solder compositions and the metal content dependence of a plating solution on the solder composition uniformity within the wafer. Experimental results show that the plating solution with the total metal concentration of more than 60 g/l gives a uniformity at eutectic point of less than 3% within wafer. In addition, we have confirmed that the use of a eutectic solder disk anode keeps the composition of a plating solution constant for a long term product run. |
| Starting Page | 293 |
| Ending Page | 298 |
| File Size | 755375 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780339290 |
| ISSN | 10898190 |
| DOI | 10.1109/IEMT.1997.626934 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-10-13 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Ultra large scale integration Flip chip Resists Shape control Gold Passivation Sputtering Lithography Cathodes Etching |
| Content Type | Text |
| Resource Type | Article |
| Subject | Industrial and Manufacturing Engineering Electrical and Electronic Engineering |
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