NDLI: Statistically calculating reject limits at parametric test

Content Provider	IEEE Xplore Digital Library
Author	Michelson, D.K.
Copyright Year	1997
Description	Author affiliation: Harris Semicond., Findlay, OH, USA (Michelson, D.K.)
Abstract	Known Good Die (KGD) methodology is a process used in the manufacture of semiconductor chips which determines reject limits for parameters measured at sample probe. The philosophy of KGD is to set reject limits on all sample probe parameters at x~/spl plusmn/4 s, where x~ is the sample average and s is the sample standard deviation, assuming a normal distribution on the parameter. When the distribution of measurements is normal, limits set at /spl plusmn/4 s correspond to a C/sub pk/ of 1.33. If the distribution of measurements is not normal, we examine using a generalized C/sub pk/ formula to find the KGD limits. KGD methods are also used to set limits at circuit probe and final test, after the chip has been packaged.
Starting Page	172
Ending Page	177
File Size	567551
Page Count	6
File Format	PDF
ISBN	0780339290
ISSN	10898190
DOI	10.1109/IEMT.1997.626895
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Probes Semiconductor device measurement Semiconductor device manufacture Gaussian distribution Fabrication Manufacturing processes Integrated circuit measurements Integrated circuit packaging Semiconductor device packaging
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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