NDLI: Active devices and wiring under chip bond pads: stress simulations and modeling methodology

Content Provider	IEEE Xplore Digital Library
Author	Awad, E.
Copyright Year	2004
Description	Author affiliation: IBM Microeletronics, Essex Junction, VT, USA (Awad, E.)
Abstract	In the semiconductor industry, cost competitiveness can be significantly improved by maximizing the use of chip real estate. For wire-bonded chips, vacant space under the bond pads can be populated with active devices and wiring known as structures under pads (SUPs). Although this layout strategy can improve productivity, reliability issues concerning stresses from the wire-bonding loads must be resolved before population can occur. The necessary qualification work, including designing, building, and stressing test sites, can become very costly if it attempts to cover all possible SUP layouts. Mechanical simulations using finite element analysis (FEA) software can play a critical role in reducing the cycle time and qualification cost by predicting the wire-bonding stresses for different SUP layouts. Knowledge gained from FEA models can be used throughout the qualification process: early on to design the test site and later on to interpret the test results and bridge them to other technologies or die configurations. To achieve these time and cost savings, a set of simulations must be properly defined and interpreted. This paper discusses mechanical modeling performed in conjunction with an SUP qualification effort at IBM. We describe the modeling methodology as well as the effects of different layout variables on the stress distribution.
Starting Page	1784
Ending Page	1787
File Size	322479
Page Count	4
File Format	PDF
ISBN	0780383656
DOI	10.1109/ECTC.2004.1320360
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wiring Bonding Stress Qualifications Costs Testing Electronics industry Productivity Buildings Analytical models
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Electromigration-limited lifetime of aluminum bond pads

The evolving standard for commercial building wiring

A new routing design methodology for multi-chip IC packages

Active device under bond pad to save I/O layout for high-pin-count SOC

Development of ultrasonic flip chip bonding for flexible printed circuit

Measurement of IP qualification costs and benefits

Thermosonic wire bonding process simulation and bond pad over active stress analysis

Flip chip ball grid array component testing under board flexure

Thermosonic Wire Bonding Process Simulation and Bond Pad Over Active Stress Analysis

Active devices and wiring under chip bond pads: stress simulations and modeling methodology

Similar Documents

Electromigration-limited lifetime of aluminum bond pads

The evolving standard for commercial building wiring

A new routing design methodology for multi-chip IC packages

Active device under bond pad to save I/O layout for high-pin-count SOC

Development of ultrasonic flip chip bonding for flexible printed circuit

Measurement of IP qualification costs and benefits

Thermosonic wire bonding process simulation and bond pad over active stress analysis

Flip chip ball grid array component testing under board flexure

Thermosonic Wire Bonding Process Simulation and Bond Pad Over Active Stress Analysis

Active devices and wiring under chip bond pads: stress simulations and modeling methodology