NDLI: A novel joint-in-via, flip-chip chip-scale package

Content Provider	IEEE Xplore Digital Library
Author	Lee, T.K. Zhang, S. Wong, C.C. Tan, A.C.
Copyright Year	2004
Abstract	It is believed that the slower-than-expected adoption of flip-chip (FC) packages is due to the lagging advancement in substrate designs and technologies with front-end processes. This lag has also resulted in the need for a costly redistribution layer (RDL), which fans out the die pads to meet the substrate design rule. This paper reviews the photographic metallization limitation of organic substrates and proposes an innovative joint-in-via architecture using existing substrate technologies to improve the pad pitch resolutions. The joint-in-via architecture consolidates the landing pads, the micro-vias, and the flip-chip joint into one common element, thereby saving valuable substrate real estate for high-density routing. It has been successfully conceptualized on a flex laminate at a pad pitch of 70 /spl mu/m and a receiving pad size of 50 /spl mu/m, potentially enabling the removal of the RDL layer for packaging. Robustness in flip-chip assembly is improved by the joint-in-via architecture because it prevents solder bridging and allows the use of existing packaging infrastructure. A new flip-chip, chip-scale package (FC-CSP) has evolved with the implementation of the joint-in-via architecture. With material optimization, the FC-CSP passes standard reliability tests, further demonstrating the robustness of the joint-in-via technology.
Starting Page	1209
Ending Page	1215
File Size	640852
Page Count	7
File Format	PDF
ISBN	0780383656
DOI	10.1109/ECTC.2004.1319065
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chip scale packaging Robustness Fans Metallization Routing Laminates Assembly Joining materials Materials reliability Materials testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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