NDLI: Clock tree structure with reduced wire length using the matched-delay skew compensation technique

Content Provider	IEEE Xplore Digital Library
Author	Esmaeili, S.E. Farhangi, A.M. Al-Khalili, A.J. Cowan, G.E.R.
Copyright Year	2012
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC, Canada (Esmaeili, S.E.; Farhangi, A.M.; Al-Khalili, A.J.; Cowan, G.E.R.)
Abstract	In this paper we propose a new approach to balance skew in the clock network by manipulating the operating speed of the flip-flop. Six versions of the master-slave flip-flop with different data to output $(T_{DQ})$ delays are used in a matched-delay skew compensation technique. The $T_{DQ}$ delay in each version of the flip-flop was increased by increasing the channel length of transistors in intermediate stages of the flip-flop. Distributing flip-flops according to their delay requirements reduces the effect of clock skew on the outputs of sequentially adjacent flip-flops. Furthermore, it increases skew bounds required by algorithms to balance the skew in the clock distribution network leading to reduced design complexity. Constructing five benchmark clock trees with a Modified Deferred Merge Embedding (MDME) algorithm with four, five, and six versions of the flip-flop shows that the matched-delay skew compensation technique can compensate for a skew up to 15% of the clock period. In addition, matched-delay skew compensation achieves a reduction in total wire length and wire elongation up to 16.6% and 56.8%, respectively, as compared to the traditional DME algorithm with only one flip-flop.
Sponsorship	IEEE Montreal Sect.
Starting Page	1
Ending Page	4
File Size	666072
Page Count	4
File Format	PDF
ISBN	9781467314312
ISSN	08407789
e-ISBN	9781467314336
e-ISBN	9781467314329
DOI	10.1109/CCECE.2012.6335054
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-29
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip-flops Clocks Delay Wires Merging Transistors Master-slave wire length Clock distribution network matched delay flip-flop skew compensation wire elongation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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