NDLI: Multi objective design space exploration of cache for embedded applications

Content Provider	IEEE Xplore Digital Library
Author	Alipour, M. Taghdisi, H. Sadeghzadeh, S.H.
Copyright Year	2012
Description	Author affiliation: Dept. of Electr., Comput. & IT Eng., Islamic Azad Univ., Qazvin, Iran (Taghdisi, H.) \|\| Dept. of Comput. & IT, Payame Noor Univ., Tehran, Iran (Sadeghzadeh, S.H.) \|\| Allameh Rafiei Higher Educ. Inst. of Qazvin, Qazvin, Iran (Alipour, M.)
Abstract	High contribution of cache access power in the total power consumption of embedded processors has made it a major concern in embedded system designs. By technology scaling, leakage power has created more stress on design constraint and power budget of embedded processors. Therefore; designers require a comprehensive design space exploration of cache architecture. In this paper we find out the optimum performance per power consumption points for cache sizes based on design space exploration using a new energy model considering dynamic and leakage energy of cache for embedded applications. Full exploration is performed based on different feature sizes to find out the effect of technology scale down on power parameters of cache. Results show that in different feature sizes 30% of static power and 43 % of total power of an embedded core is consumed in the cache hierarchy in average. It means based on this work in smaller feature sizes and for embedded application that can tolerate performance lose up to 3%, we should select smaller cache hierarchy to deliver better performance per power as the most important parameter in designing embedded systems.
Sponsorship	IEEE Montreal Sect.
Starting Page	1
Ending Page	4
File Size	776523
Page Count	4
File Format	PDF
ISBN	9781467314312
ISSN	08407789
e-ISBN	9781467314336
e-ISBN	9781467314329
DOI	10.1109/CCECE.2012.6334940
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-29
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Power demand Embedded systems Energy consumption Space exploration Computer architecture Conferences performance per power Embedded processor design space exploration cache
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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