NDLI: A cost effective implementation of 8×8 transform of HEVC from H.264/AVC

Content Provider	IEEE Xplore Digital Library
Author	Martuza, M. Wahid, K.
Copyright Year	2012
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Saskatchewan, Saskatoon, SK, Canada (Martuza, M.; Wahid, K.)
Abstract	The state of the art video standard H.264/AVC is very popular worldwide for its efficient coding techniques. But recently the ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Moving Picture Expert Group (MPEG) have been jointly developing the next generation video standard, called High Efficiency Video Coding (HEVC) which is expected to be more efficient in coding video. In this paper, we present a shared architecture which can compute the 8×8 Inverse Discrete Cosine Transform (IDCT) of the HEVC from that of the H.264/AVC using a new mapping technique. The hardware share approach ensures the maximum circuits reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18um technology. The results show that the proposed design has the maximum decoding capability of 67fps for 1080p full HD video.
Sponsorship	IEEE Montreal Sect.
Starting Page	1
Ending Page	4
File Size	714114
Page Count	4
File Format	PDF
ISBN	9781467314312
ISSN	08407789
e-ISBN	9781467314336
e-ISBN	9781467314329
DOI	10.1109/CCECE.2012.6334911
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-29
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Video coding Computer architecture Standards Adders Transforms Decoding Transform coding H.264/AVC 8×8 Inverse Integer Transform Multi standard IDCT HEVC
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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