NDLI: Amulti-level phase/frequency detector for clock and data recoveryapplications

Content Provider	IEEE Xplore Digital Library
Author	Jingcheng Zhuang Kwasniewski, T.
Copyright Year	2005
Description	Author affiliation: Dept. of Electron., Carleton Univ., Ottawa, Ont. (Jingcheng Zhuang; Kwasniewski, T.)
Abstract	A clock and data recovery circuit is an important building block in data communication systems and the phase detector (PD) is one of the critical parts of a CDR. A bang-bang phase detector is suitable for low-power high-bit-rate operation, but a separate frequency detector (FD) has to be used for frequency acquisition, which results in some problems such as frequency drift, sudden phase jump due to the disaccord of the PD and FD. To solve these problems, this paper proposes a novel phase/frequency detector (PFD) with an extended operating range and a multiple-level output for half-rate CDR applications. Because of its multiple-level output, the CDR can achieve lower output clock jitter than a conventional binary PD. The proposed PFD has an operating speed comparable to conventional bang-bang PDs and can also be used in full-rate CDRs with minor modification. The simulation of a half-rate CDR model employing this type of PFD confirms the feasibility of the proposed PFD
Starting Page	828
Ending Page	830
File Size	149955
Page Count	3
File Format	PDF
ISBN	0780388852
ISSN	08407789
DOI	10.1109/CCECE.2005.1557056
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-01
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase detection Phase frequency detector Clocks Voltage-controlled oscillators Data communication Switches Filters Jitter Circuit simulation Sampling methods
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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