NDLI: A 1.8 V 1.1 GHz novel digital multiplier

Content Provider	IEEE Xplore Digital Library
Author	Khatibzadeh, A.A. Raahemifar, K. Ahmadi, M.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput., Ryerson Univ., Toronto, Ont. (Khatibzadeh, A.A.; Raahemifar, K.)
Abstract	This paper presents the design of an 8 times 8-bit novel digital multiplier providing a better performance than the conventional linear array multipliers in two folds of speed and power consumption. The modified pairwise and parallel addition algorithms provide high speed multiplication in this work. The power performance of individual block is pre-evaluated to identify the most power consuming element and attempt is to select the most efficient topology to reduce the power consumption of entire multiplier while maintaining the high operating frequency. The proposed multiplier has been designed and implemented employing TSMC 0.18 mum CMOS technology and analyzed using HSPICE. When the multiplier is targeted to a maximum operating frequency of 1.1 GHz at $V_{DD}$ equal to 1.8 V, it dissipates 22 mW. For comparison purposes a Baugh-Wooley multiplier is redesigned and optimized. The simulation results are compared showing superiority of proposed multiplier in both power and speed performance
Starting Page	686
Ending Page	689
File Size	404458
Page Count	4
File Format	PDF
ISBN	0780388852
ISSN	08407789
DOI	10.1109/CCECE.2005.1557022
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-01
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing algorithms Digital signal processing Encoding Energy consumption Topology Frequency CMOS technology Iterative algorithms Computer architecture Next generation networking
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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