NDLI: Real time 3D rendering patch processing using an embedded SIMD computer architecture

Content Provider	IEEE Xplore Digital Library
Author	Mrochuk, J.S. Elliott, D.G.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta. (Mrochuk, J.S.; Elliott, D.G.)
Abstract	This paper demonstrates that three dimensional imaging operations can benefit from the parallel processing provided by a single instruction multiple data (SIMD) processing array. The SIMD array used for implementation is a processor in memory architecture created by Atsana Semiconductor. This design is used in Atsana's J2210 media processor, which is used as the test platform for this project. The J2210 is a system on a chip containing an ARMtrade microprocessor and a SIMD array processor. The goal is to test this SIMD architecture for suitability as a hardware acceleration system for real time rendering of 3D scenes in an embedded platform. SIMD architectures take advantage of data parallelism, which is readily available in 3D rendering
Starting Page	743
Ending Page	746
File Size	255278
Page Count	4
File Format	PDF
ISBN	0780388852
ISSN	08407789
DOI	10.1109/CCECE.2005.1557036
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-01
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Rendering (computer graphics) Hardware Graphics Layout Embedded system Power system analysis computing Energy consumption Parallel processing Microprocessors
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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