NDLI: Digital Systems Architectures Based on On-line Checkers

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Table of contents

Message from the Program Chair

Message from the General and Organizing Chairs

Conference Committees

Keynote Abstract: Rich Goldman

Keynote Abstract: Alessandro Cremonesi

Keynote Abstract: Thomas Williams

Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform

Network Interface Sharing Techniques for Area Optimized NoC Architectures

Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links

CART: Communication-Aware Routing Technique for Application-Specific NoCs

LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control

Flexible Baseband Architectures for Future Wireless Systems

A Lightweight Operating Environment for Next Generation Cognitive Radios

On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip

A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity Analysis

Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems

Digital Systems Architectures Based on On-line Checkers

Fault Models and Injection Strategies in SystemC Specifications

An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA

Experimental SEU Impact on Digital Design Implemented in FPGAs

Temperature and Leakage Aware Power Control for Embedded Streaming Applications

Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software

Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations

A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips

A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching

A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures

A Modular Approach to Model Heterogeneous MPSoC at Cycle Level

Performance and Timing Yield Enhancement using Highway-on-Chip Planning

An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures

Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units

Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture

Design of a Two Dimensional PRSI Image Processor

A Hardware Design for Camera-Based Power Management of Computer Monitor

Co-design and Implementation of the H.264/AVC Motion Estimation Algorithm Using Co-simulation

A Low-Cost Cache Coherence Verification Method for Snooping Systems

Dependability Evaluation of Real Railway Interlocking Device

Formulating MITF for a Multicore Processor with SEU Tolerance

Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip

Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs

Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology

Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis

Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing

Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?

Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations

Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits

Leveraging Data Promotion for Low Power D-NUCA Caches

Revisiting the Cache Effect on Multicore Multithreaded Network Processors

Using Empirical Science to Engineer Systems: Optimizing Cache for Power and Performance

Reducing Leakage through Filter Cache

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures

Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications

Virtual Scan Chains for Online Testing of FPGA-based Embedded Systems

Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication

Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools

PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism

Digital Nuclear Magnetic Resonance Acquisition Channel

Fast FPGA-based Trigger and Data Acquisition System for the CERN Experiment NA62: Architecture and Algorithms

A Novel Digital Ultrasound System for Experimental Research Activities

A Parallel and Modular Architecture for 802.16e LDPC Codes

WirelessUSB – Performance Analysis of an Embedded System in a Peer-to-Peer Application

Design of a Distributed Embedded System for Domotic Applications

An Embedded Acquisition System for Remote Monitoring of Tire Status in F1 Race Cars through Thermal Images

Design of a High Performance Traffic Generator on Network Processor

Implementation of Microprogrammed Hard Disk Drive Servo Sequencer

Quantum-Dot Cellular Automata Serial Comparator

Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization

Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits

Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm

Technology Library Modelling for Information-driven Circuit Synthesis

Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics

A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis

A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks

A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance

Exploiting WSN for Audio Surveillance Applications: The VoWSN Approach

Code Generation from Statecharts: Simulation of Wireless Sensor Networks

Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking

How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design

An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty

SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation

VLSI Implementation of a Cryptography-Oriented Reconfigurable Array

A New Array Fabric for Coarse-Grained Reconfigurable Architecture

Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration

System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments

IRIS: A Firmware Design Methodology for SIMD Architectures

Measurement, Analysis and Modeling of RTOS System Calls Timing

Development of Functional Delay Tests

Application Analysis for Parallel Processing

Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration

Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor

Exploring ISS Abstractions for Embedded Software Design

High Performance Computing for Embedded System Design: A Case Study

Automatic Identification of Parallelism in Handel-C

A Variable Length Vector Pipeline Architecture Design Methodology

Ultra-Low Power Passive UHF RFID for Wireless Sensor Networks

Models and Tradeoffs in WSN System-Level Design

Pearson–based Analysis of Positioning Error Distribution in Wireless Sensor Networks

On the Need for Passive Monitoring in Sensor Networks

Efficient Test Pattern Compression Method Using Hard Fault Preferring

Digital Implementation of a BIST Method based on Binary Observations

Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification

Power Conscious RTL Test Scheduling

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC

Functional Verification of a USB Host Controller

An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra

On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components

A New Rounding Algorithm for Variable Latency Division and Square Root Implementations

An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences

Logic Transformations by Multiple Wire Network Addition

On Projecting Sums of Products

On Lookup Table Cascade-Based Realizations of Arbiters

A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits

A Wireless Sensor Platform for Assistive Technology Applications

Reliable Data Transmission over Simple Wireless Channels: A Case Study

A Long-term Wearable Vital Signs Monitoring System using BSN

Design of an Ultra Low-Power RFID Baseband Processor Featuring an AES Cryptography Engine

Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard

Architecture of a Power-Gated Wireless Sensor Node

A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors

Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool

TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path

Embedded Diagnostic Logic Test Exploiting Regularity

On the Complexity of Error Detection Functions for Redundant Residue Number Systems

Programmable Numerical Function Generators for Two-Variable Functions

SIMD Enhancements for a Hough Transform Implementation

Hardware-oriented Adaptation of a Particle Swarm Optimization Algorithm for Object Detection

Acceleration of Smith-Waterman using Recursive Variable Expansion

Maximizing Resource Utilization by Slicing of Superscalar Architecture

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

9th EUROMICRO Conference on Digital System Design (DSD'06)

8th Euromicro Conference on Digital System Design (DSD'05)

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

Euromicro Symposium on Digital System Design, 2003. Proceedings.

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

Proceedings Euromicro Symposium on Digital Systems Design

Digital Systems Architectures Based on On-line Checkers

Content Provider	IEEE Xplore Digital Library
Author	Straka, M. Kotasek, Z. Winter, J.
Copyright Year	2008
Description	Author affiliation: Fac. of Inf. Technol., Brno Univ. of Technol., Brno (Straka, M.; Kotasek, Z.; Winter, J.)
Abstract	In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the design of Fault Tolerant Systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented.
Starting Page	81
Ending Page	87
File Size	181314
Page Count	7
File Format	PDF
ISBN	9780769532776
DOI	10.1109/DSD.2008.42
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-03
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital systems Circuit testing Protocols Fault tolerant systems Design methodology Hardware Redundancy Circuit faults System testing Specification languages VHDL Fault tolerant system on-line checker circuit protocol PSL FPGA
Content Type	Text
Resource Type	Article

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