NDLI: An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences

Content Provider	IEEE Xplore Digital Library
Author	Matutino, P.M. Sousa, L.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., IST / INESC-ID, Lisbon (Sousa, L.) \|\| Dept. of Electron., ISEL / INESC-ID, Lisbon (Matutino, P.M.)
Abstract	The sum of absolute differences (SAD) is a distance metric commonly used to determine the similarity between two data sets. A very recent method for directly comparing the magnitude of two numbers represented in residue number systems (RNS) leads to the possibility of using modular arithmetic to compute the SAD. In this paper we propose an efficient hardware SAD unit that computes this Manhattan distance independently of each RNS channel. Therefore, the processing time can be reduced by simultaneously exploiting the carry-free characteristic of the modular arithmetic and the new method proposed by the authors of this paper to compare the magnitude of numbers in RNS. The proposed architecture is suitable to implement SAD units in application specific integrated circuit (ASIC) and in field programmable gate array (FPGA). In order to evaluate the performance of the proposed structures a hardware processor for computing the minimum SAD was implemented in a FPGA and ASIC. From the experimental results it was possible to obtain operating frequencies above 200 MHz for XILINX FPGAs XC2VP50-7 and XC4VLX80-12, and 300 MHz for the ASIC implementation. These results allow the implementation of real-time motion estimators for high resolution images according to the most recent standards for video coding.
Starting Page	768
Ending Page	775
File Size	232067
Page Count	8
File Format	PDF
ISBN	9780769532776
DOI	10.1109/DSD.2008.107
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-03
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Application specific integrated circuits Arithmetic Computer architecture Hardware Telecommunication computing Motion estimation Video coding Digital systems Design methodology Motion Estimation Residue Number System Application specific processor Field Programmable Gate Arrays (FPGA) Application Specific Integrated Circuit (ASIC)
Content Type	Text
Resource Type	Article

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