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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Monchiero, M. Palermo, G. Silvano, C. Villa, O. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dipt. di Elettron. e Inf., Politec. di Milano, Milan (Palermo, G.; Silvano, C.) || HP Labs., Palo Alto, CA (Monchiero, M.) || Paciflc Northwest Nat. Lab., Richland, WA (Villa, O.) |
| Abstract | This paper proposes a system-level cycle-based framework to model and design heterogeneous multiprocessor systems-on-chip (MPSoC), called GRAPES. The approach features flexibility and modularity maintaining high simulation speed despite modeling at cycle level. Intellectual property (IP) system modules can be described as C++or System C entities and they are wrapped into C++ objects, called plug-ins. Plug-ins, that are modeled by the transaction level modeling (TLM) style, are managed by the GRAPES kernel, which is the core of the simulation framework. GRAPES structural approach permits to easily model run-time reconfiguration and power modeling. Furthermore, GRAPES has been used to model and to simulate a case study: a scalable and heterogeneous MPSoC based on network-on-chip (NoC) interconnect. |
| Starting Page | 158 |
| Ending Page | 164 |
| File Size | 335400 |
| Page Count | 7 |
| File Format | |
| ISBN | 9780769532776 |
| DOI | 10.1109/DSD.2008.84 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-09-03 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Object oriented modeling Pipelines Kernel Power system modeling Multiprocessing systems Protocols System-on-a-chip Network-on-a-chip Hardware Digital systems Multiprocessor System-on Chip (MPSoC) Simulation Modeling System-on-Chip (SoC) |
| Content Type | Text |
| Resource Type | Article |
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