NDLI: Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip

Content Provider	IEEE Xplore Digital Library
Author	Fuchs, G. Fugger, M. Schmid, U. Steininger, A.
Copyright Year	2008
Description	Author affiliation: Embedded Comput. Syst. Group, Vienna Univ. of Technol., Vienna (Fuchs, G.; Fugger, M.; Schmid, U.; Steininger, A.)
Abstract	Systems on chip (SoC) have much in common with traditional (networked) distributed systems in that they consist of largely independent components with dedicated communication interfaces. Therefore the adoption of classic distributed algorithms for SoCs suggests itself. The implementation complexity of these algorithms, however, significantly depends on the underlying failure models. In traditional software-based solutions this is normally not an issue, such that the most unconstrained, namely the Byzantine, failure model is often applied here. Our case study of a hardware implemented tick synchronization algorithm shows, however, that in an SoC-implementation substantial hardware savings can result from restricting the failure model to benign failures (omissions, crashes). On the downside, it turns out that such restricted failure models have a fairly poor coverage with respect to the hardware faults occurring in practice, and that additional measures to enforce these restrictions may entail an implementation overhead that outweighs the gain obtained in the implementation of a simpler algorithm. As a remedy we investigate the potential of failure transformation in this context and show that this technique may indeed yield an optimized overall solution.
Starting Page	242
Ending Page	249
File Size	267829
Page Count	8
File Format	PDF
ISBN	9780769532776
DOI	10.1109/DSD.2008.65
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-03
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerant systems Distributed algorithms System-on-a-chip Clocks Circuit faults Very large scale integration Synchronization Hardware Fault tolerance Digital circuits fault-tolerant hardware failure models failure transformations fault-tolerant distributed algorithms
Content Type	Text
Resource Type	Article

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