NDLI: Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing

Content Provider	IEEE Xplore Digital Library
Author	Ghavami, B. Khosraviani, M. Pedram, H.
Copyright Year	2008
Description	Author affiliation: Comput. Eng. Dept., Amirkabir Univ. of Technol., Tehran (Ghavami, B.; Khosraviani, M.; Pedram, H.)
Abstract	Minimizing power consumption is one of the most important objectives in VLSI design. This paper introduces a methodology for the optimization of total power consumption of template based asynchronous circuits via dual $V_{dd}$ assignment, dual $V_{th}$ assignment and template sizing while maintaining performance requirements. The utilized circuit model is a Timed Petri-net which captures the dynamic behavior of the circuit. These three power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 65 nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty. From the experimental results, we show that the combination of asynchronous design and three low power techniques is an effective way to achieve low power and high performance circuits.
Starting Page	274
Ending Page	281
File Size	457777
Page Count	8
File Format	PDF
ISBN	9780769532776
DOI	10.1109/DSD.2008.89
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-03
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Asynchronous circuits Energy consumption Threshold voltage Optimization methods Clocks Very large scale integration Genetic algorithms Power dissipation Timing Frequency synchronization Quantum Genetic Algorithm Asynchronous Circuits Low Power Design Dual Vdd Dual Vth Sizing Timed Petri-Net
Content Type	Text
Resource Type	Article

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