NDLI: Formation of sub-10 nm width InGaAs finFETs of 200 nm height by atomic layer epitaxy

Content Provider	IEEE Xplore Digital Library
Author	Cohen-Elias, D. Law, J.J.M. Chiang, H.W. Sivananthan, A. Zhang, C. Thibeault, B.J. Mitchell, W.J. Lee, S. Carter, A.D. Huang, C.-Y. Chobpattana, V. Stemmer, S. Keller, S. Rodwell, M.J.W.
Copyright Year	2013
Description	Author affiliation: ECE Dept., Univ. of California, Santa Barbara, Santa Barbara, CA, USA (Cohen-Elias, D.; Law, J.J.M.; Chiang, H.W.; Sivananthan, A.; Zhang, C.; Thibeault, B.J.; Mitchell, W.J.; Lee, S.; Carter, A.D.; Huang, C.-Y.; Keller, S.; Rodwell, M.J.W.) \|\| Mater. Dept., Univ. of California, Santa Barbara, Santa Barbara, CA, USA (Chobpattana, V.; Stemmer, S.)
Abstract	As FETs are scaled, the dielectric and semiconductor channel thicknesses must be reduced to suppress short-channel effects. Even using fin field effect transistors (finFETs) and gate all around FETs (GAAFETs), [1],[2], whose electrostatic performance is excellent, at 4nm gate length the channel should be less than 2nm thick. To obtain high drive current per unit IC die area, the fin height should be many times the fin pitch, i.e. tens to hundreds of nm. Dry-etching a fin of few-nm width and > 100 nm height presents severe challenges in control of etch sidewall slope and in minimizing surface damage. Here we report an InGaAs finFET fabrication flow which form fins of sub-10nm width and 200 nm height. Fin width is controlled by atomic layer epitaxial (ALE) growth and by semiconductor selective crystallographic wet etching. We further demonstrate self-aligned source-drain regrowth in this process [3],[4]. This facilitates scaling of the source/drain pitch to small dimensions.
Starting Page	1
Ending Page	2
File Size	387194
Page Count	2
File Format	PDF
ISBN	9781479908110
ISSN	15483770
e-ISBN	9781479908141
DOI	10.1109/DRC.2013.6633884
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Indium phosphide Indium gallium arsenide Logic gates Silicon compounds Tin FinFETs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Quantum-size effects in sub 10-nm fin width InGaAs FinFETs

An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

Fabrication of InGaAs quantum wire structures by As/sub 2/ flux in molecular beam epitaxy

12 nm-gate-length ultrathin-body InGaAs/InAs MOSFETs with $8.3•10^{5}$ ION/IOFF

Performance evaluation of 90 nm InGaAs HEMTs

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

Variability characterisation of nanoscale Si and InGaAs FinFETs at subthreshold

InGaAs quasi-quantum-wire FET on V-grooved substrate by selective growth with As/sub 2/ flux in hydrogen-assisted molecular beam epitaxy

Asymmetric InGaAs MOSFETs with InGaAs source and InP drain

Formation of sub-10 nm width InGaAs finFETs of 200 nm height by atomic layer epitaxy

Similar Documents

Quantum-size effects in sub 10-nm fin width InGaAs FinFETs

An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

Fabrication of InGaAs quantum wire structures by As/sub 2/ flux in molecular beam epitaxy

12 nm-gate-length ultrathin-body InGaAs/InAs MOSFETs with $8.3•10^{5}$ ION/IOFF

Performance evaluation of 90 nm InGaAs HEMTs

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

Variability characterisation of nanoscale Si and InGaAs FinFETs at subthreshold

InGaAs quasi-quantum-wire FET on V-grooved substrate by selective growth with As/sub 2/ flux in hydrogen-assisted molecular beam epitaxy

Asymmetric InGaAs MOSFETs with InGaAs source and InP drain

Formation of sub-10 nm width InGaAs finFETs of 200 nm height by atomic layer epitaxy