NDLI: Magnetic logic and computation using magnetic tunnel junctions

Content Provider	IEEE Xplore Digital Library
Author	Jian-Ping Wang
Copyright Year	2013
Description	Author affiliation: Electr. & Comput. Eng. Dept., Univ. of Minnesota, Minneapolis, MN, USA (Jian-Ping Wang)
Abstract	An energy efficient logic device for the post-CMOS era has been the goal of a variety of research fields. The limits of scaling, which we expect to reach by the year 2025, demand that future advances in computational power will not be realized from ever-shrinking device sizes, but rather by innovative designs and new physics. Magnetic tunnel junction has been a promising candidate for future integrated magnetic memory and computation because its unique functionalities [1]. The need for the intermediate circuitry for MTJ based logic hinders fan-out function, adds integration complexity, power consumption, area and delay overheads to logic modules. In this paper, first I will report a recent design of the Magnetic Tunnel Junction-Based Spintronic Logic Units (ALU) and the fabrication of a multiple MTJ based logic circuit which computes logic functions while transferring the data to the next logic gate [2,3,4]. This MTJ logic circuit can perform Majority, AND, OR, NAND, and NOR operations. I will also report a recent design and demonstration of MTJ based nanomagnetic logic (NML), which is nonvolatile and lower power [5]. A key requirement for logic devices is an electrical based input/output (I/O) scheme in order to interface with supplementary electrical components. I will discuss the experimental demonstration of the electrical reading and spin transfer torque programming of dipole coupled nanomagnets using magnetic tunnel junctions (MTJs) [5]. The STT write incorporated a clocking field utilized for magnetic logic applications. For 10-15 nm spacing between nanomagnets, 50 nm × 80 nm and 70 nm × 100 nm, currents of 100-200 μA a re sufficient to program the device.
Starting Page	175
Ending Page	176
File Size	675544
Page Count	2
File Format	PDF
ISBN	9781479908110
ISSN	15483770
e-ISBN	9781479908141
DOI	10.1109/DRC.2013.6633850
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Magnetic tunneling Junctions Magnetoelectronics Torque Magnetic devices Logic devices
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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