NDLI: Dual-gate MOSFETs on monolayer CVD MoS2 films

Content Provider	IEEE Xplore Digital Library
Author	Liu, H. Si, M. Najmaei, S. Neal, A.T. Du, Y. Ajayan, P.M. Lou, J. Ye, P.D.
Copyright Year	2013
Description	Author affiliation: Dept. of Mech. Eng. & Mater. Sci., Rice Univ., Houston, TX, USA (Najmaei, S.; Ajayan, P.M.; Lou, J.) \|\| Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Liu, H.; Si, M.; Neal, A.T.; Du, Y.; Ye, P.D.)
Abstract	Monolayer $MoS_{2}$ with a direct band gap of 1.8 eV is a promising two-dimensional material with a potential to surpass graphene in next generation nanoelectronic applications.[1-3] We have synthesized monolayer $MoS_{2}$ thin films via chemical vapor deposition (CVD) method on $Si/SiO_{2}$ substrate and comprehensively study the device performance and variation on dual-gated $MoS_{2}$ field-effect transistors. Over 100 devices are studied to obtain a statistical description of device performance on monolayer CVD $MoS_{2}.$ We have achieved record high drain current of 62.5 mA/mm in CVD monolayer $MoS_{2}$ films ever reported.[4] We further extract the intrinsic contact resistance of low work function metal Ti on monolayer CVD $MoS_{2}$ with an expectation value of 175 Ω·mm, which can be significantly decreased to 10 Ω·mm by appropriate gating. By taking the impact of contact resistance into account, average and max intrinsic field-effect mobility is estimated to be 13.0 and 21.6 $cm^{2}/V·s$ in monolayer CVD $MoS_{2}$ films.
Starting Page	163
Ending Page	164
File Size	1030166
Page Count	2
File Format	PDF
ISBN	9781479908110
ISSN	15483770
e-ISBN	9781479908141
DOI	10.1109/DRC.2013.6633844
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Films Contact resistance MOSFET Educational institutions Performance evaluation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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