NDLI: Performance enhancement of gate-all-around InGaAs nanowire MOSFETs by raised source and drain structure

Content Provider	IEEE Xplore Digital Library
Author	Si, M. Lou, X. Li, X. Gu, J.J. Wu, H. Wang, X. Zhang, J. Gordon, R.G. Ye, P.D.
Copyright Year	2013
Description	Author affiliation: Dept. of Chem. & Chem. Biol., Harvard Univ., Cambridge, MA, USA (Lou, X.; Wang, X.; Gordon, R.G.) \|\| Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Si, M.; Li, X.; Gu, J.J.; Wu, H.; Zhang, J.; Ye, P.D.)
Abstract	InGaAs gate-all-around (GAA) MOSFETs with implanted source and drain (S/D) structure have been demonstrated which offer large drive currents and excellent immunity to short channel effects down to deep sub-100 nm channel length [1-2]. In this work, we fabricate $n^{++}$ raised S/D InGaAs GAA MOSFETs with 10nm or 20nm thick nanowires and 200nm channel length. Maximum $I_{on}$ over 1 mA/μm at $V_{gs}-V_{t}=1V$ and $V_{ds}=1V$ is obtained, which is attributed to small S/D series resistance $(R_{sd}).$ The $R_{sd}$ of small dimension devices is systematically studied. We find that $R_{sd}$ is significantly reduced with the $n^{++}$ S/D structure compare to the implanted structure [1]. At the same time, we find that $R_{sd}$ is inverse proportional to the perimeter of the nanowire on 20nm thick nanowire devices while $R_{sd}$ is inverse proportional to the cross section area of the nanowire on 10nm thick nanowire devices. The significant difference confirms that the 10nm thick nanowire works in volume inversion mode while the 20nm nanowire or larger dimension still works in surface inversion mode.
Starting Page	19
Ending Page	20
File Size	888525
Page Count	2
File Format	PDF
ISBN	9781479908110
ISSN	15483770
e-ISBN	9781479908141
DOI	10.1109/DRC.2013.6633774
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nanoscale devices Nanobioscience Indium gallium arsenide MOSFET Logic gates Educational institutions Immune system
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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