NDLI: Performance impact of post-regrowth channel etching on InGaAs MOSFETs having MOCVD source-drain regrowth

Content Provider	IEEE Xplore Digital Library
Author	Carter, A.D. Lee, S. Elias, D.C. Huang, C.-Y. Law, J.J.M. Mitchell, W.J. Thibeault, B.J. Chobpattana, V. Stemmer, S. Gossard, A.C. Rodwell, M.J.W.
Copyright Year	2013
Description	Author affiliation: ECE Dept., Univ. of California, Santa Barbara, Santa Barbara, CA, USA (Carter, A.D.; Lee, S.; Elias, D.C.; Huang, C.-Y.; Law, J.J.M.; Mitchell, W.J.; Thibeault, B.J.; Gossard, A.C.; Rodwell, M.J.W.) \|\| Mater. Dept., Univ. of California, Santa Barbara, Santa Barbara, CA, USA (Chobpattana, V.; Stemmer, S.)
Abstract	Given low interface trap densities and low access resistances, InGaAs MOSFETs can provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT), and are thus strong candidates for use in $VLSI.^{1}$ Transconductance as high as 2.1 mS/μm $(V_{ds}=0.5$ V) with 115 mV/decade $(V_{ds}=0.5$ V) subthreshold swing has been $reported^{2}$ in planar III-V MOSFETs using a gate recess etch through the N+ InGaAs contact layer. It remains to be established whether the necessary etch depth control can be obtained at VLSI integration scales and 10-20 nm gate lengths. Using self-aligned regrowth of the N+ source and drain, III-V MOSFETs can be fabricated without requiring this gate recess $etch;^{3}$ 1.9 mS/μm $(V_{d}$ =1 V) with 116 mV/decade $(V_{ds}=0.05$ V) subthreshold swing was reported in a 55 nm $L_{g}$ InGaAs MOSFET with MOCVD source-drain $regrowth.^{4}$ Note that no post-regrowth etching of the channel surface is reported in (4). We have recently $found^{5}$ that InGaAs MOSFETs using MBE source-drain regrowth, subthreshold swing and transconductance are substantially improved by removing a 5 nm N+ InGaAs channel cap post-regrowth and immediately prior to gate dielectric deposition, suggesting damage to the channel surface during regrowth. Here, we report similar findings for MOCVD regrowth. We fabricated 65 nm $L_{g}$ $In_{0}._{53}Ga_{0.47}As$ surface-channel MOSFETs in a gate-last process with self-aligned raised InGaAs S/D access regions formed by MOCVD regrowth. Removal of ~ 2.4 nm of the channel surface by digital etching improved the transconductance from 1.1 to 1.58 mS/μm (65 nm $L_{g}$ $V_{d}=0.5$ V), and reduced the subthreshold swing from 326 to 110 mV/dec (1 μm $L_{g},$ $V_{ds}=0.05$ V). These results suggest that substantial surface damage arises, and must be addressed, in MOCVD regrowth III-V MOSFET processes.
Starting Page	23
Ending Page	24
File Size	285214
Page Count	2
File Format	PDF
ISBN	9781479908110
ISSN	15483770
e-ISBN	9781479908141
DOI	10.1109/DRC.2013.6633776
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Etching Indium gallium arsenide MOSFET MOCVD
Content Type	Text
Resource Type	Article

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