NDLI: Spintronic logic gates for spintronic data using magnetic tunnel junctions

Content Provider	IEEE Xplore Digital Library
Author	Patil, S. Lyle, A. Harms, J. Lilja, D.J. Jian-Ping Wang
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Minnesota Twin Cities, USA (Patil, S.; Lyle, A.; Harms, J.; Lilja, D.J.; Jian-Ping Wang)
Abstract	The emerging field of spintronics is undergoing exciting developments with the advances recently seen in spintronic devices, such as magnetic tunnel junctions (MTJs). While they make excellent memory devices, recently they have also been used to accomplish logic functions. The properties of MTJs are greatly different from those of electronic devices like CMOS semiconductors. This makes it challenging to design circuits that can efficiently leverage the spintronic capabilities. The current approaches to achieving logic functionality with MTJs include designing an integrated CMOS and MTJ circuit, where CMOS devices are used for implementing the required intermediate read and write circuitry. The problem with this approach is that such intermediate circuitry adds overheads of area, delay and power consumption to the logic circuit. In this paper, we present a circuit to accomplish logic operations using MTJs on data that is stored in other MTJs, without an intermediate electronic circuitry. This thus reduces the performance overheads of the spintronic circuit while also simplifying fabrication. With this circuit, we discuss the notion of performing logic operations with a non-volatile memory device and compare it with the traditional method of computation with separate logic and memory units. We find that the MTJ-based logic unit has the potential to offer a higher energy-delay efficiency than that of a CMOS-based logic operation on data stored in a separate memory module.
Starting Page	125
Ending Page	131
File Size	2199964
Page Count	7
File Format	PDF
ISBN	9781424489367
ISSN	10636404
e-ISBN	9781424489374
DOI	10.1109/ICCD.2010.5647611
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-03
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Magnetic tunneling Magnetoelectronics Resistance Random access memory Delay Performance evaluation Integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in