NDLI: Influence of InP source/drain layers upon the DC characteristics of InAs/InGaAs MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Cheng-Ying Huang Sanghoon Lee Elias, D.C. Law, J.J.M. Chobpattana, V. Stemmer, S. Gossard, A.C. Rodwell, M.J.W.
Copyright Year	2014
Description	Author affiliation: Mater. Dept., Univ. of California, Santa Barbara, Santa Barbara, CA, USA (Chobpattana, V.; Stemmer, S.)
Abstract	Because of the low effective mass, MOSFETs using In-rich (x>53%) $In_{x}Ga_{1-x}As$ channels [1-5] exhibit high on-state current $I_{on}$ at low drain bias $(V_{DS}=0.5$ V). However, the small bandgap of high-indium $In_{x}Ga_{1-x}As$ channels can lead to high off-state leakage $I_{off}$ due to band-to-band tunneling (BTBT) and impact ionization (I.I.). Earlier we had reported [1] that adding an unintentionally-doped (U.I.D.) InGaAs vertical spacer within the raised source/drain (S/D) of an InAs/InGaAs channel MOSFET substantially reduced $I_{off}.$ Here we compare the characteristics of FETs using a wide-bandgap U.I.D. InP vertical spacer to earlier results [1] using an InGaAs spacer, and to control devices using only a very thin spacer. We find that FETs using InP spacers have $I_{off}$ comparable to FETs using narrower-bandgap InGaAs spacers of similar thickness, suggesting that with the spacer, the observed $I_{off}$ at high $V_{DS}$ arises from BTBT or I.I. within the channel, and not within the high-field gate-drain spacer layer. Further, the wide-gap U.I.D. InP source spacer does not increase the threshold voltage $V_{th},$ suggesting that the gated potential barrier remains in the channel and not in the source spacer region. We also compare the on-state characteristics of FETs using InAs/InGaAs channels and an N+ InP S/D. Unlike the findings of [6], we do not observe improved $I_{on}$ with the use of a wider-bandgap N+ source.
Starting Page	225
Ending Page	226
File Size	222685
Page Count	2
File Format	PDF
ISBN	9781479954056
e-ISBN	9781479954063
DOI	10.1109/DRC.2014.6872379
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Indium gallium arsenide Indium phosphide Logic gates Gold MOSFET
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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