NDLI: Digital bit stream jitter testing using jitter expansion

Content Provider	IEEE Xplore Digital Library
Author	Hyun Choi Chatterjee, A.
Copyright Year	2008
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA (Hyun Choi; Chatterjee, A.)
Abstract	This paper presents a time-domain jitter expansion technique for high-speed digital bit sequence jitter testing. While jitter expansion has been applied to phase noise measurements of sinusoidal signals before, its applicability to random clock jitter testing and data-dependent jitter testing have not been explored. The latter problems have wide application and necessitate new analysis procedures given in this paper. Since low phase noise sinusoids can be generated relatively easily as compared to low jitter digital clocks, the proposed technique utilizes a low-frequency sine wave as a reference signal which can be fed to the device under test with less concern for reference signal noise. A special circuit called a jitter-sensor is used for jitter extraction and produces a low-speed output signal with higher jitter values that track the jitter of the high-speed digital test signal. Thus, conventional narrow-bandwidth testers are able to analyze the sensor output. This allows high resolution jitter testing for high-speed digital signals possible at low cost.
Starting Page	1468
Ending Page	1473
File Size	4050586
Page Count	6
File Format	PDF
ISBN	9783981080131
DOI	10.1109/DATE.2008.4484881
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-10
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Jitter Circuit testing Phase noise Clocks Time domain analysis Noise measurement Phase measurement Signal generators Circuit noise Low-frequency noise
Content Type	Text
Resource Type	Article

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