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Content Provider | IEEE Xplore Digital Library |
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Author | Kleanthous, M. Sazeides, Y. |
Copyright Year | 2008 |
Description | Author affiliation: Dept. of Comput. Sci., Univ. of Cyprus, Nicosia (Kleanthous, M.; Sazeides, Y.) |
Abstract | Cache-Content-Duplication (CCD) occurs when there is a miss for a block in a cache and the entire content of the missed block is already in the cache in a block with a different tag. Caches aware of content-duplication can have lower miss rates by allowing only blocks with unique content to enter a cache. This work examines the potential of CCD for instruction caches. We show that CCD is a frequent phenomenon and that an idealized duplication- detection mechanism for instruction caches has the potential to increase performance of an out-of-order processor, with a 2-way eight instruction per block 16 KB instruction cache, often by more than 5% and up to 20%. This work also proposes CATCH, a hardware based mechanism for dynamically detecting CCD. Experimental results for an out-of-order processor show that a CATCH with a 2.32 KB cost usually captures 60% or more of the CCD's idealized potential. |
Starting Page | 1426 |
Ending Page | 1431 |
File Size | 360262 |
Page Count | 6 |
File Format | |
ISBN | 9783981080131 |
DOI | 10.1109/DATE.2008.4484874 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2008-03-10 |
Publisher Place | Germany |
Access Restriction | Subscribed |
Rights Holder | European Design Automation Association (EDAA) |
Subject Keyword | Charge coupled devices Hardware Compaction Out of order Costs User-generated content Program processors Application software Computer science Delay |
Content Type | Text |
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