NDLI: Performance Analysis of SoC Architectures Based on Latency-Rate Servers

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2008 Design, Automation and Test in Europe

Design, Automation and Test in Europe [Title page]

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Table of contents

DATE Executive Committee

DATE Sponsor Committee

Technical Programme Committee

Technical Programme Topic Chairs

Best Paper Awards

Automatically Realising Embedded Systems from High-Level Functional Models

Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems

System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures

Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level

Power Gating for Ultra-low Leakage: Physics, Design, and Analysis

Heterogeneous System-level Specification Using SystemC

Power-Aware Testing and Test Strategies for Low Power Devices

From Transistor to PLL - Analogue Design and EDA Methods

DfM in the Analogue and Digital World

Formal Methods in System and MpSoC Performance Analysis and Optimisation

Soft Errors: System Effects, Protection Techniques and Case Studies

EDAA/DATE PhD Forum

Call for Papers

Designing Micro/Nano Systems for a Safer and Healthier Tomorrow

Perspective on Embedded Systems: Challenges, Solutions and Research Priorities

Cycle-approximate Retargetable Performance Estimation at the Transaction Level

A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip

Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation

Tailored Solutions for Safety-Installations in the Loetschberg Tunnel - A Project with Importance for the Trans-European Rail Traffic

On the Verification of High-Order Constraint Compliance in IC Design

Industrial IP integration flows based on IP-XACT standards

A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment

Using Reconfigurable Logic to Optimise GPU Memory Accesses

Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs

Design flow for embedded FPGAs based on a flexible architecture template

Optimal High-Resolution Spectral Analyzer

A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation

Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters

Practical Implementation of a Network Analyzer for Analog BIST Applications

Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures

Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices

A Framework of Stochastic Power Management Using Hidden Markov Model

Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement

An Efficient Solar Energy Harvester for Wireless Sensor Nodes

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization

Parametric Throughput Analysis of Synchronous Data Flow Graphs

Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling

SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder

Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN

Sizing Rules for Bipolar Analog Circuit Design

Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density

A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits

Symbolic Reliability Analysis and Optimization of ECU Networks

Verification of Temporal Properties in Automotive Embedded Software

A Novel Approach for EMI Design of Power Electronics

Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments

Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns

An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers

Performance Analysis of SoC Architectures Based on Latency-Rate Servers

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs

Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC)

Architecture Exploration of NAND Flash-based Multimedia Card

Resilient Dynamic Power Management under Uncertainty

Robust and Low Complexity Rate Control for Solar Powered Sensors

Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting

Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution

Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs

A Formal Approach To The Protocol Converter Problem

Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip

Synthesizing Synchronous Elastic Flow Networks

Periodic Steady-State Analysis Augmented with Design Equality Constraints

Analysis of Oscillator Injection Locking by Harmonic Balance Method

Model Checking of Analog Systems using an Analog Specification Language

Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications

Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring

Guiding Circuit Level Fault-Tolerance Design with Statistical Methods

A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements

Towards fault tolerant parallel prefix adders in nanoelectronic systems

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking

Embedded Tutorial - Software for Wireless Networked Embedded Systems

Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction

A Scalable Algorithmic Framework for Row-Based Power-Gating

Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting

Physical Architectures of Automotive Systems

A Mutation Model for the SystemC TLM 2.0 Communication Interfaces

Efficient Design Validation Based on Cultural Algorithms

Algorithms for Maximum Satisfiability using Unsatisfiable Cores

In-band Cross-Trigger Event Transmission for Transaction-Based Debug

Efficient Representation and Analysis of Power Grids

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate

ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis

Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods

Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures

Vectorization of Reed Solomon Decoding and Mapping on the EVP

A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder

Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction

Scan Chain Organization for Embedded Diagnosis

State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores

Automated Testability Enhancements for Logic Brick Libraries

A Game-Theoretic Approach to Real-Time System Testing

Modeling Event Stream Hierarchies with Hierarchical Event Models

Semantics for Model-Based Validation of Continuous/Discrete Systems

Using UML as Front-end for Heterogeneous Software Code Generation Strategies

Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm

Software Components for Reliable Automotive Systems

Model-Based-Design Is Nice But...

A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems

Signal Probability Based Statistical Timing Analysis

A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect

Current source based standard cell model for accurate signal integrity and timing analysis

An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation

SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction

Transistor-Specific Delay Modeling for SSTA

Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications

A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms

Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA

On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits

Optimal Margin Computation for At-Speed Test

Resistive Bridging Fault Simulation of Industrial Circuits

Physically-Aware N-Detect Test Pattern Selection

Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication

Constraint Refinement for Online Verifiable Cross-Layer System Adaptation

Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload

Embedded Tutorial - ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe

Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures

Random Stimulus Generation using Entropy and XOR Constraints

MCjammer: Adaptive Verification for Multi-core Designs

Efficient Implementation of Native Software Simulation for MPSoC

Simulation-Directed Invariant Mining for Software Verification

Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation

A Novel Technique for Improving Temperature Independency of Ring-ADC

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs

Integrated approach to energy harvester mixed technology modelling and performance optimisation

A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers

A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio

Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios

Test Strategies for Low Power Devices

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures

A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs

Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis

Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set

Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency

Instruction Set Extension Exploration in Multiple-Issue Architecture

Instruction Re-encoding Facilitating Dense Embedded Code

Panel Session - The Future Car: Technology, Methods and Tools

Improving Constant-Coefficient Multiplier Verification by Partial Product Identification

Improved Visibility in One-to-Many Trace Concretization

Efficient Symbolic Simulation of Low Level Software

Completeness in SMT-based BMC for Software Programs

Novel Pin Assignment Algorithms for Components with Very High Pin Counts

A Generic Standard Cell Design Methodology for Differential Circuit Styles

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices

Exploiting Correlation Kernels for Ef£cient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing

A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications

Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement

Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment

A Programmable and Low-EMI Integrated Half-Bridge Driver in BCD Technology

CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology

A low-cost concurrent error detection technique for processor control logic

Approximate logic circuits for low overhead, non-intrusive concurrent error detection

Logical Reliability of Interacting Real-Time Tasks

Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints

Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems

Compositional design of isochronous systems

Quantitative Productivity Measurement in IC Design

Determining the Technical Complexity of Integrated Circuits

Qalitative and Quantitative Analysis of IC Designs

Capturing and Analyzing IC Design Productivity Metrics

Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits

Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity Considerations

Implications of Technology Trends on System Dependability

Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges

Software Protection Mechanisms for Dependable Systems

Subsystem Exchange in a Concurrent Design Process Environment

Cooperative Safety: a Combination of Multiple Technologies

System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style

Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints

A Single-supply True Voltage Level Shifter

Clock Distribution Scheme using Coplanar Transmission Lines

Compositional, dynamic cache management for embedded chip multiprocessors

Comparison of memory write policies for NoC based Multicore Cache Coherent Systems

Serialized Asynchronous Links for NoC

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits

Quantified Synthesis of Reversible Logic

Adaptive Simulation for Single-Electron Devices

OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks

Improvements in Polynomial-Time Feasibility Testing for EDF

A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications

An application-based EDF scheduler for OSEK/VDX

Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme

Simultaneous FU and Register Binding Based on Network Flow Method

A Variation Aware High Level Synthesis Framework

EPIC: Ending Piracy of Integrated Circuits

Specification and Design Considerations for Reliable Embedded Systems

Synthesis of Fault-Tolerant Embedded Systems

Reliable Services in an Imperfect World

Video Processing Requirements on SoC Infrastructures

Memory Technology for Extended Large-Scale Integration in Future Electronics Applications

Memory-aware NoC Exploration and Design

Incremental Criticality and Yield Gradients

Latch Modeling for Statistical Timing Analysis

Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis

Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor

Operating System Controlled Processor-Memory Bus Encryption

An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation

Multi-Vector Tests: A Path to Perfect Error-Rate Testing

iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing

Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors

Instruction Cache Energy Saving Through Compiler Way-Placement

Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints

Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications

Automatic Selection of Application-Specific Reconfigurable Processor Extensions

An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications

Dependability for high-tech systems: an industry-as-laboratory approach

User-Aware Dynamic Task Allocation in Networks-on-Chip

Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures

An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication

Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design

Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming

An adaptable FPGA-based System for Regular Expression Matching

Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems

Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis

Power Balanced Gates Insensitive to Routing Capacitance Mismatch

On Analysis and Synthesis of (n,k)-Non-Linear Feedback Shift Registers

FPGA Design for Algebraic Tori-Based Public-Key Cryptography

Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation

Functional Self-Testing for Bus-Based Symmetric Multiprocessors

Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality

Advanced Analog Filters for Telecommunications

Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies

Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces

High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures

Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence

Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems

Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor

Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems

Multicast Parallel Pipeline Router Architecture for Network-on-Chip

Variation tolerant NoC design by means of self-calibrating links

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs

Developing Mesochronous Synchronizers to Enable 3D NoCs

Memory Organization with Multi-Pattern Parallel Accesses

CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches

Magellan: A Search and Machine Learning-based Framework for Fast Multi-core Design Space Exploration and Optimization

Process Variation Aware Issue Queue Design

Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array

GMDS: Hardware implementation of novel real output queuing architecture

Front End Device for Content Networking

Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography

Digital bit stream jitter testing using jitter expansion

A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution

A Design-for-Diagnosis Technique for SRAM Write Drivers

Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications

Retargetable Code Optimization for Predicated Execution

Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads

Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams

ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis

HOT TOPIC - 3D Integration or How to Scale in the 21st Century

Built-in Clock Skew System for On-line Debug and Repair

Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects

On Automated Trigger Event Generation in Post-Silicon Validation

Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems

Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking

Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration

Merged Computation for Whirlpool Hashing

Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor

Safe Automatic Flight Back and Landing of Aircraft Flight Reconfiguration Function (FRF)

PWM-based test stimuli generation for BIST of high resolution ΣΔ ADCs

Fault Clustering in deep-submicron CMOS Processes

Energy Efficient and High Speed On-Chip Ternary Bus

Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems

Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches

Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression

A methodology for improving software design lifecycle in embedded control systems

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network

A System Architecture for Reconfigurable Trusted Platforms

Automatic Generation of Complex Properties for Hardware Designs

Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices

A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs

Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication

Accuracy-Adaptive Simulation of Transaction Level Models

Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor

Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture

Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology

A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design

Re-Examining the Use of Network-on-Chip as Test Access Mechanism

VLSI implementation of SISO arithmetic decoders for joint source channel coding

Error Detection/Correction in DNA Algorithmic Self-Assembly

Temperature-Aware Voltage Selection for Energy Optimization

A Fast Approximation Algorithm for MIN-ONE SAT

Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis

An efficient algorithm for free resources management on the FPGA

Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits

Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs

CARbridge, Reduction of System Complexity by Standardisation of the System-Basis-Chips for Automotive Applications

Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications

Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme

Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs

Adaptive Filesystem Compression for Embedded Systems

Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits

TinyTimber, Reactive Objects in C for Real-Time Embedded Systems

Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications

Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications

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Performance Analysis of SoC Architectures Based on Latency-Rate Servers

Content Provider	IEEE Xplore Digital Library
Author	Vink, J.P. van Berkel, K. van der Wolf, P.
Copyright Year	2008
Description	Author affiliation: Eindhoven Univ. of Technol., Eindhoven (Vink, J.P.)
Abstract	This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. A multi-channel DVB-T set-top box case study demonstrates the power of the method. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.
Starting Page	200
Ending Page	205
File Size	841551
Page Count	6
File Format	PDF
ISBN	9783981080131
DOI	10.1109/DATE.2008.4484686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-10
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Performance analysis Calculus Telecommunication traffic Delay Network servers Traffic control Digital video broadcasting Upper bound Power system interconnection Heart
Content Type	Text
Resource Type	Article

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