NDLI: Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures

Content Provider	IEEE Xplore Digital Library
Author	Al Faruque, M.A. Henkel, J.
Copyright Year	2008
Description	Author affiliation: CES - Dept. for Embedded Syst., Karlsruhe Univ., Karlsruhe (Al Faruque, M.A.; Henkel, J.)
Abstract	We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the router in a NoC) used to implement logical channels multiplexed across the physical channel in a router output port for QoS supported on-chip communication. In the first step, the number of virtual channels is minimized during the mapping of tasks to the NoC at the design time of a system on chip (SoC)for which we use a swarm intelligence-based ant colony optimization (ACO) algorithm. In the second step, a probabilistic approach based on the traffic model of the application is used to further minimize the number of virtual channels. We achieve on average 90.2% reduction in the number of virtual channels compared to a fixed state- of-the-art (i.e. QNoC) allocation for the E3S embedded application benchmark suit. The reduction depends on the designer and the QoS parameter, and it is dependent on the specific application driven traffic model. We demonstrate our design space exploration by means of a complete robot application and also extend our exploration by evaluating the E3S embedded application benchmark suit.
Starting Page	1238
Ending Page	1243
File Size	360725
Page Count	6
File Format	PDF
ISBN	9783981080131
DOI	10.1109/DATE.2008.4484848
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-10
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Space exploration Network-on-a-chip Traffic control Design methodology Design optimization Algorithm design and analysis System-on-a-chip Particle swarm optimization Ant colony optimization Orbital robotics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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