NDLI: A custom-cell identification method for high-performance mixed standard/custom-cell designs

Content Provider	IEEE Xplore Digital Library
Author	Lo, J.Y.-L. Wu-An Kuo Wu, A.C.-H. TingTing Hwang
Copyright Year	2003
Description	Author affiliation: Comput. Sci. Dept., Tsing Hua Univ., Hsin-Chu, Taiwan (Lo, J.Y.-L.; Wu-An Kuo; Wu, A.C.-H.; TingTing Hwang)
Abstract	This paper describes a design method targeted to mixed standard- and custom-cells which is carried out as follows. First, it generates a standard-cell design to obtain a maximal achievable speed. Second, it performs a cell customization process to determine which standard cells need to be customized in order to satisfy the given timing constraint. Once designers select a set of standard cells to be customized, they define the specification of the custom cells and develop the cells accordingly. Finally, the designers replace the standard cells with the custom ones and re-evaluate the speed of the design. The customization process continues until the timing constraint is satisfied. In this paper, we present a custom-cell identification method for high-speed datapath-oriented designs. The proposed method uses an HDL-based standard-cell design flow by integrating a custom-cell identification algorithm to determine a minimal-cost cell set and the design budgets for cell customization. Experimental results on a set of benchmarking designs are reported to demonstrate the effectiveness of the proposed method.
Sponsorship	EDAA EDA Consortium IEEE Comput. Soc. TTTC IEEE Comput. Soc. DATC ECSI ACM/SIGDA RAS
Starting Page	1102
Ending Page	1103
File Size	229903
Page Count	2
File Format	PDF
ISBN	0769518702
ISSN	15301591
DOI	10.1109/DATE.2003.1253754
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-07
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Design methodology Costs Libraries Delay Algorithm design and analysis Logic design Process design Circuit synthesis Standards development
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An efficient contact placement for custom cell layout synthesis

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs

Physical synthesis methodology for high performance microprocessors

SOC-driven design methodology for full custom high performance mixed-signal designs

A semi-custom design flow in high-performance microprocessor design

Performance-Effective Compaction of Standard-Cell Libraries for Digital Design

Optimal P/N width ratio selection for standard cell libraries

Custom cell development for standard cell designs

Custom digital cell generation flow for 65nm processes

A custom-cell identification method for high-performance mixed standard/custom-cell designs

Similar Documents

An efficient contact placement for custom cell layout synthesis

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs

Physical synthesis methodology for high performance microprocessors

SOC-driven design methodology for full custom high performance mixed-signal designs

A semi-custom design flow in high-performance microprocessor design

Performance-Effective Compaction of Standard-Cell Libraries for Digital Design

Optimal P/N width ratio selection for standard cell libraries

Custom cell development for standard cell designs

Custom digital cell generation flow for 65nm processes

A custom-cell identification method for high-performance mixed standard/custom-cell designs