NDLI: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs

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IC Design Challenges for Ambient Intelligence

Semiconductor Challenges

Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts

Improving the Efficiency of Memory Partitioning by Address Clustering

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors

Power Efficiency through Application-Specific Instruction Memory Transformations

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures

Circuit and Platform Design Challenges in Technologies beyond 90nm

Global Wire Bus Configuration with Minimum Delay Uncertainty

Timing Verification with Crosstalk for Transparently Latched Circuits

Statistical Timing Analysis Using Bounds

Reduced Delay Uncertainty in High Performance Clock Distribution Networks

Scaling into Ambient Intelligence

Masking the Energy Behavior of DES Encryption

Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems

Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications

Virtual Compression through Test Vector Stitching for Scan Based Designs

Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture

A Technique for High Ratio LZW Compression

Fast Computation of Data Correlation Using BDDs

RTOS Modeling for System Level Design

Modeling and Integration of Peripheral Devices in Embedded Systems

Systemic Embedded Software Generation from SystemC

Noise Macromodel for Radio Frequency Integrated Circuits

Approximation Approach for Timing Jitter Characterization in Circuit Simulators

A Model of Computation for Continuous-Time "-" Modulators

Behavioural Modelling and Simulation of Modulators Using Hardware Description Languages

Securing Mobile Appliances: New Challenges for the System Designer

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

A General Framework for Analysing System Properties in Platform-Based Embedded System Designs

Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration

Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures

DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers

Extending JTAG for Testing Signal Integrity in SoCs

EBIST: A Novel Test Generator with Built-In Fault Detection Capability

A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis

Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors

A New Simulation Technique for Periodic Small-Signal Analysis

Generalized Posynomial Performance Modeling

HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits

High-Level Allocation to Minimize Internal Hardware Wastage

Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units

Automated Bus Generation for Multiprocessor SoC Design

Online Scheduling for Block-Partitioned Reconfigurable Devices

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems

A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms

A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification

Non-Enumerative Path Delay Fault Diagnosis

Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step

Introduction to Hardware Abstraction Layers for SoC

Hardware/Software Partitioning of Operating Systems

Embedded Software in Digital AM-FM Chipset

Packetized On-Chip Interconnect Communication Analysis for MPSoC

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors

Development and Application of Design Transformations in ForSyDe

System Level Specification in Lava

Formal Semantics of Synchronous SystemC

Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated

SystemC-AMS Requirements, Design Objectives and Rationale

Parallel Processing Architectures for Reconfigurable Systems

Different Approaches to Add Reconfigurability in a SoC Architecture

A Lightweight Approach for Embedded Reconfiguration of FPGAs

Creating Value Through Test

Control Flow Driven Splitting of Loop Nests at the Source Code Level

Data Space Oriented Scheduling in Embedded Systems

Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling

Time Budgeting in a Wireplanning Context

Interconnect Planning with Local Area Constrained Retiming

A Novel Metric for Interconnect Architecture Performance

Specification of Non-Functional Intellectual Property Components

Profile-Driven Selective Code Compression

Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver

Panel Title: Reconfigurable Computing " Different Perspectives

RF-BIST: Loopback Spectral Signature Analysis

Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation

On Modeling Cross-Talk Faults

Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops

Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications

Runtime Code Parallelization for On-Chip Multiprocessors

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms

Modeling and Evaluation of Substrate Noise Induced by Interconnects

Model-Order Reduction Based on PRONY's Method

Combined FDTD/Macromodel Simulation of Interconnected Digital Devices

Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses

Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer

Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation

Instruction Set Emulation for Rapid Prototyping of SoCs

Hardware/Software Design Space Exploration for a Reconfigurable Processor

From C Programs to the Configure-Execute Model

FPGA-Based Implementation of a Serial RSA Processor

Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair

Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric

An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor

High Speed and Highly Testable Parallel Two-Rail Code Checker

Safe Automotive Software Development

Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits

Linear Model-Based Error Identification and Calibration for Data Converters

Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters

Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver

Analytical Design Space Exploration of Caches for Embedded Systems

Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs

Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform

A First Step Towards Hw/Sw Partitioning of UML Specifications

Multi-Granularity Metrics for the Era of Strongly Personalized SOCs

Energy Estimation for Extensible Processors

Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures

Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface

MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems

Low-Cost Software-Based Self-Testing of RISC Processor Cores

A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories

Test Data Compression: The System Integrator's Perspective

Time Domain Multiplexed TAM: Implementation and Comparison

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization

Delay Fault Testing of Core-Based Systems-on-a-Chip

Reducing Multi-Valued Algebraic Operations to Binary

Combination of Lower Bounds in Exact BDD Minimization

Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation

Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation

On-Chip Stochastic Communication

An Integrated Approach for Improving Cache Behavior

Rapid Configuration and Instruction Selection for an ASIP: A Case Study

Local Search for Boolean Relations on the Basis of Unit Propagation

Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis

Efficient Preimage Computation Using A Novel Success-Driven ATPG

Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol

Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions

Hot Topic Session: RF Design Technology for Highly Integrated Communication Systems

Power/Ground Mesh Area Optimization Using Multigrid-Based Technique

A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees

Crosstalk Reduction in Area Routing

Area Fill Generation With Inherent Data Volume Reduction

Transaction Based Design: Another Buzzword or the Solution to a Design Problem?

Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications

Verification of Proofs of Unsatisfiability for CNF Formulas

A Circuit SAT Solver With Signal Correlation Guided Learning

Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals

Generalized Data Transformations for Enhancing Cache Behavior

Software Streaming via Block Streaming

Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems

Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design

STG Optimisation in the Direct Mapping of Asynchronous Circuits

Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues

Dynamic Tool Integration in Heterogeneous Computer Networks

Layered, Multi-Threaded, High-Level Performance Design

A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities

Processor/Memory Co-Exploration on Multiple Abstraction Levels

Run-Time Management of Logic Resources on Reconfigurable Systems

Managing a Reconfigurable Processor in a General Purpose Workstation Environment

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip

RTL Test Pattern Generation for High Quality Loosely Deterministic BIST

A New Approach to Test Generation and Test Compaction for Scan Circuits

Fully Automatic Test Program Generation for Microprocessor Cores

On the Characterization of Hard-to-Detect Bridging Faults

The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method

Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching

A Fast Algorithm for the Layout Based Electro-Thermal Simulation

Platform-Based Testbench Generation

Software Architectural Transformations: A New Approach to Low Energy Embedded Software

Dynamic Functional Unit Assignment for Low Power

Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy

Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors

Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations

Mesh Partitioning Approach to Energy Efficient Data Layout

On-chip Stack Based Memory Organization for Low Power Embedded Architectures

Figure of Merit Based Selection of A/D Converters

XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines

Multithreaded Synchronous Data Flow Simulation

PLFire: A Visualization Tool for Asynchronous Phased Logic Designs

Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering

Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs

Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration

LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks

Symbolic Analysis of Nonlinear Analog Circuits

Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects

A New Crosstalk Noise Model for DOMINO Logic Circuits

Modeling Noise Transfer Characteristic of Dynamic Logic Gates

Heterogeneous Programmable Logic Block Architectures

An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration

Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs

Mapping Applications to an FPFA Tile

Load Distribution with the Proximity Congestion Awareness in a Network on Chip

Micro-Network for SoC: Implementation of a 32-Port SPIN network

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems

Library Functions Timing Characterization for Source-Level Analysis

G-MAC: An Application-Specific MAC/Co-Processor Synthesizer

Power Constrained High-Level Synthesis of Battery Powered Digital Systems

PARLAK: Parametrized Lock Cache Generator

A Secure Web-Based Framework for Electronic System Level Design

Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor

Compiler Support for Reducing Leakage Energy Consumption

An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems

Decomposition of Extended Finite State Machine for Low Power Design

Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations

Using RTL Statespace Information and State Encoding for Induction Based Property Checking

Combining Simulation and Guided Traversal for the Verification of Concurrent Systems

Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies

Self-Testing Embedded Checkers for Bose-Lin, Bose,and a Class of Borden Codes

Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees

SAT-Based Techniques in System Synthesis

Refinement of Mixed-Signal Systems with SystemC

Polychrony for Refinement-Based Design

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula

Consequences of RAM Bitline Twisting for Test Coverage

An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme

Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG

Comparison of Test Pattern Decompression Techniques

Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST

Test Data Compression Based on Output Dependence

A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs

Content Provider	ACM Digital Library
Author	Kuo, Wu-An Wu, Allen C. -H. Lo, Jennifer Y. -L Hwang, Ting Ting
Abstract	Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath designs is the full-custom design method targeted to bit-sliced or bit-alignment layout architectures. Using this approach, designers can fully exploit design properties, such as various circuit designs, structural regularities and layout structures, to develop high-speed, low-power and high-density datapath designs. However, the main drawbacks of this approach are threefold: (1) extremely high development cost, (2) very long development time, and (3) difficult to migrate the custom design to a new technology. The other approach is the HDL-based synthesis method targeted to the standard-cell layout architecture. This approach is highly productive and easy to implement. However, due to lack of the ability to exploit the regularity properties of datapath designs, itýs mostly suitable to produce low/medium-speed datapath designs. Another design method targeted to mixed standard-and custom-cells is carried out as follows. First, it generates a standard-cell design to obtain a maximal achievable speed. Second, it performs a cell customization process to determine which standard cells need to be customized in order to satisfy the given timing constraint. This cell customization process is usually performed incrementally based on designersý intuitions and experiences. Once designers select a set of standard cells to be customized, they will define the specification of the custom cells and develop the cells accordingly. Finally, the designers will replace the standard cells with the custom ones and re-evaluate the speed of the design. The customization process will continue until the timing constraint is satisfied. In this paper, we present a custom-cell identification method for high-speed datapath-oriented designs. The proposed method uses an HDL-based standard-cell design flow by integrating a custom-cell identification algorithm to determine a minimal-cost cell set and the design budgets for cell customization. Experimental results on a set of benchmarking designs are reported to demonstrate the effectiveness of the proposed method. Note that our problem is different from the cell-sizing problem. While the cell-sizing problem is to select and to replace (re-size) cells (instances of cells in cell library) one by one, our problem is to select and re-design cells in the cell library and to replace all instances of the cell in the design at one time.
File Format	PDF
ISBN	0769518702
ISSN	15301591
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-03-03
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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