NDLI: Synthesis of application-specific highly-efficient multi-mode systems for low-power applications

Content Provider	IEEE Xplore Digital Library
Author	Lih-Yih Chiou Bhunia, S. Roy, K.
Copyright Year	2003
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Lih-Yih Chiou; Bhunia, S.; Roy, K.)
Abstract	We present a novel design methodology for synthesizing multiple configurations (or modes) into a single programmable system. Many DSP and multimedia applications require reconfigurability of a system along with efficiency in terms of power performance and area. FPGAs provide a reconfigurable platform, however, they are slower in speed with significantly higher power consumption than achievable by a customized ASIC. In this work, we have developed techniques to realize an efficient reconfigurable system for a set of user-specified configurations. A data flow graph transformation method coupled with efficient scheduling and allocation are used to automatically synthesize the system from its behavioral level specifications. Experimental results on several applications demonstrate that we can achieve about 60/spl times/ power reduction on average with about 4/spl times/ improvement in performance over corresponding FPGA implementations.
Sponsorship	EDAA EDA Consortium IEEE Comput. Soc. TTTC IEEE Comput. Soc. DATC ECSI ACM/SIGDA RAS
Starting Page	96
Ending Page	101
File Size	279378
Page Count	6
File Format	PDF
ISBN	0769518702
ISSN	15301591
DOI	10.1109/DATE.2003.1253593
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-07
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Application specific integrated circuits Application software Digital signal processing Hardware Design methodology Multimedia systems Energy consumption Design optimization Logic arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Hardware/Software Co-reconfigurable Multimedia Architecture

Performance trade-offs for hardware/software implementation of a fuzzy logic controller on programmable hardware

The use of field programmable gate arrays in high performance radar signal processing applications

Context-based ASIC synthesis

Multiplication and inner product with field programmable gate arrays

Synthesis for FPGAs: an overview

Efficient application of modern logic synthesis in FPGA-based designing of information and signal processing systems

Tradeoff analysis of integer multiplier circuits implemented in FPGAs

Programmable DSP systems using FPGA

Synthesis of application-specific highly-efficient multi-mode systems for low-power applications

Similar Documents

A Hardware/Software Co-reconfigurable Multimedia Architecture

Performance trade-offs for hardware/software implementation of a fuzzy logic controller on programmable hardware

The use of field programmable gate arrays in high performance radar signal processing applications

Context-based ASIC synthesis

Multiplication and inner product with field programmable gate arrays

Synthesis for FPGAs: an overview

Efficient application of modern logic synthesis in FPGA-based designing of information and signal processing systems

Tradeoff analysis of integer multiplier circuits implemented in FPGAs

Programmable DSP systems using FPGA

Synthesis of application-specific highly-efficient multi-mode systems for low-power applications