NDLI: On-chip stack based memory organization for low power embedded architectures

Content Provider	IEEE Xplore Digital Library
Author	Mamidipaka, M. Dutt, N.
Copyright Year	2003
Description	Author affiliation: Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA (Mamidipaka, M.; Dutt, N.)
Abstract	This paper presents an on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded-systems use the notion of stack for implementation of function calls. However such stack data is stored in processor address space, typically in the main memory and accessed through caches. Our analysis of several benchmarks show that the callee saved registers and return addresses for function calls constitute a significant portion of the total memory accesses. We propose a separate stack-based memory organization to store these registers and return addresses. Our experimental results show that effective use of such stack-based memories yield significant reductions in system power/energy, while simultaneously improving the system performance. Application of our approach to the SPECint95 and MediaBench benchmark suites show up to 32.5% reduction in energy in L1 data caches, with marginal improvements in system performance.
Sponsorship	EDAA EDA Consortium IEEE Comput. Soc. TTTC IEEE Comput. Soc. DATC ECSI ACM/SIGDA RAS
Starting Page	1082
Ending Page	1087
File Size	413363
Page Count	6
File Format	PDF
ISBN	0769518702
ISSN	15301591
DOI	10.1109/DATE.2003.1253748
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-07
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded system Registers Computer architecture Energy dissipation Energy consumption Power dissipation System performance Batteries Programming Proposals
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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