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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gehm Moraes, F. Mesquita, D. Carlos Palma, J. Moller, L. Calazans, N. |
| Copyright Year | 2003 |
| Description | Author affiliation: Faculdade de Informatica, PUCRS, Porto Alegre, Brazil (Gehm Moraes, F.; Mesquita, D.; Carlos Palma, J.; Moller, L.; Calazans, N.) |
| Abstract | This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. The main goal is to present a set of tools for remote and partial reconfiguration developed for the Virtex FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGAs. |
| Sponsorship | EDAA EDA Consortium IEEE Comput. Soc. TTTC IEEE Comput. Soc. DATC ECSI ACM/SIGDA RAS |
| Starting Page | 1122 |
| Ending Page | 1123 |
| File Size | 395594 |
| Page Count | 2 |
| File Format | |
| ISBN | 0769518702 |
| ISSN | 15301591 |
| DOI | 10.1109/DATE.2003.1253763 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-03-07 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Circuits Logic devices Reconfigurable logic Computer architecture Platform virtualization Pipelines Read only memory HTML Buildings |
| Content Type | Text |
| Resource Type | Article |
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