NDLI: TEASE: A systematic analysis framework for early evaluation of FinFET-based advanced technology nodes

Content Provider	IEEE Xplore Digital Library
Author	Mallik, A. Zuber, P. Tsung-Te Liu Chava, B. Ballal, B. Del Bario, P.R. Baert, R. Croes, K. Ryckaert, J. Badaroglu, M. Mercha, A. Verkest, D.
Copyright Year	2013
Description	Author affiliation: IMEC, Leuven, Belgium (Mallik, A.; Zuber, P.; Tsung-Te Liu; Chava, B.; Ballal, B.; Del Bario, P.R.; Baert, R.; Croes, K.; Ryckaert, J.; Badaroglu, M.; Mercha, A.; Verkest, D.)
Abstract	This paper proposes TEASE (Technology Exploration and Analysis for SoC-level Evaluation), a framework to systematically analyze and evaluate system design in finFET-based technology node. The proposed framework combines both lithography and electrical constraints of a particular technology node to optimize the standard cell library performance. Growing complexity of logic design at nodes below 20nm causes to adopt a design style that can embrace the simplicity required to enable manufacturing, along with a process technology that can be finely tuned to the desired performance constraints. Additionally, the introduction of finFET based devices poses a new challenge for the designers to come up with an efficient standard cell template. The proposed framework can be used to detect the technology constraints that act as the bottleneck for the enablement of design at these advanced nodes. Results presented in this paper show by optimizing these bottlenecks we can improve the performance of a standard cell library significantly. Furthermore, adapting to such an analysis framework at an early stage of technology development helps to take the design constraints into the decision loop for realization of technology research into real products.
Starting Page	1
Ending Page	6
File Size	1906864
Page Count	6
File Format	PDF
ISBN	9781450320719
ISSN	0738100X
DOI	10.1145/2463209.2488764
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Computer architecture Microprocessors Standards Libraries Optimization Metals System-on-chip SoC evaluation FinFET technology standard cell architecture
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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