NDLI: Dynamic voltage and frequency scaling for shared resources in multicore processor designs

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2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

Proceedings of the 50th Design Automation $Conference^{®}$

Mapping on multi/many-core systems: Survey of current and emerging trends

Workload and user experience-aware Dynamic Reliability Management in multicore processors

Liveness evaluation of a Cyclo-Static DataFlow Graph

Double patterning lithography-aware analog placement

Simultaneous analog placement and routing with current flow and current density considerations

Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits

Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine

Dynamic behavior of cell signaling networks - Model design and analysis automation

Defect tolerance in nanodevice-based programmable interconnects: Utilization beyond avoidance

An efficient and effective analytical placer for FPGAs

Throughput-oriented kernel porting onto FPGAs

Memory partitioning for multidimensional arrays in high-level synthesis

Balancing security and utility in Medical Devices?

Towards trustworthy medical devices and body area networks

Low-energy encryption for medical devices: Security adds an extra design dimension

Aging-aware compiler-directed VLIW assignment for GPGPU architectures

Exploiting program-level masking and error propagation for constrained reliability optimization

REGIMap: Register-aware application mapping on Coarse-Grained Reconfigurable Architectures (CGRAs)

Polyhedral model based mapping optimization of loop nests for CGRAs

Improving energy gains of inexact DSP hardware through reciprocative error compensation

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

XDRA: Exploration and optimization of last-level cache for energy reduction in DDR DRAMs

Towards variation-aware system-level power estimation of DRAMs: An empirical approach

TEASE: A systematic analysis framework for early evaluation of FinFET-based advanced technology nodes

Stitch-aware routing for multiple e-beam lithography

Automatic design rule correction in presence of multiple grids and track patterns

Multiple chip planning for chip-interposer codesign

GPU-based N-detect transition fault ATPG

Post-silicon conformance checking with virtual prototypes

On testing timing-speculative circuits

An ATE assisted DFD technique for Volume Diagnosis of scan chains

Predicting future technology performance

Predicting future product performance: Modeling and evaluation of standard cells in FinFET technologies

The ITRS design technology and system drivers roadmap: Process and status

Proactive circuit allocation in multiplane NoCs

A heterogeneous multiple network-on-chip design: An application-aware approach

Designing energy-efficient NoC for real-time embedded systems through slack optimization

RISO: Relaxed network-on-chip isolation for cloud processors

Smart hill climbing for agile dynamic mapping in many-core systems

HCI-Tolerant NoC router microarchitecture

Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures

LEQA: Latency estimation for a quantum algorithm mapped to a quantum circuit fabric

Pareto epsilon-dominance and identifiable solutions for BioCAD modeling

Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations

Gene modification identification under flux capacity uncertainty

A field-programmable pin-constrained digital microfluidic biochip

BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition

Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures

Synthesis of feedback decoders for initialized encoders

On learning-based methods for design-space exploration with High-Level Synthesis

Runtime dependency analysis for loop pipelining in High-Level Synthesis

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Cross-layer racetrack memory design for ultra high density and low power consumption

Improving the energy efficiency of hardware-assisted watchpoint systems

Low-power area-efficient large-scale ip lookup engine based on binary-weighted clustered networks

Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints

Improving charging efficiency with workload scheduling in energy harvesting embedded systems

Creation of ESL power models for communication architectures using automatic calibration

A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique

RESP: A robust Physical Unclonable Function retrofitted into embedded SRAM array

VeriTrust: Verification for hardware trust

RASTER: Runtime adaptive spatial/temporal error resiliency for embedded processors

ABCD-L: Approximating continuous linear systems using Boolean models

Bayesian Model Fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data

Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis

Machine-learning-based hotspot detection using topological classification and critical feature extraction

A novel fuzzy matching model for lithography hotspot detection

An efficient layout decomposition approach for Triple Patterning Lithography

E-BLOW: E-beam lithography overlapping aware stencil planning for MCC system

Automatic clustering of wafer spatial signatures

Multidimensional analog test metrics estimation using extreme value theory and statistical blockade

High-throughput TSV testing and characterization for 3D integration using thermal mapping

On effective and efficient in-field TSV repair for stacked 3D ICs

Cloud platforms and embedded computing - The operating systems of the future

Tessellation: Refactoring the OS around explicit resource containers with continuous adaptation

The Autonomic Operating System research project - Achievements and future directions

Role of power grid in side channel attack and power-grid-aware secure design

NumChecker: Detecting kernel control-flow modifying rootkits by using Hardware Performance Counters

High-performance hardware monitors to protect network processors from data plane attacks

Compiler-based side channel vulnerability analysis and optimized countermeasures application

Lighting the dark silicon by exploiting heterogeneity on future processors

Simultaneous multithreading support in embedded distributed memory MPSoCs

APPLE: Adaptive Performance-Predictable Low-Energy caches for reliable hybrid voltage operation

An optimized page translation for mobile virtualization

Scalable vectorless power grid current integrity verification

Constraint abstraction for vectorless power grid verification

The impact of electromigration in copper interconnects on power grid integrity

TinySPICE: A parallel SPICE simulator on GPU for massively repeated small circuit simulations

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem

Smart non-default routing for clock power reduction

Routing congestion estimation with real design constraints

Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

21st century digital design tools

System architecture and software design for Electric Vehicles

Model-based development and verification of control software for electric vehicles

Hybrid energy storage systems and battery management for electric vehicles

Reliability challenges for electric vehicles: From devices to architecture and systems software

Reliable on-chip systems in the nano-era: Lessons learnt and future trends

A layout-based approach for Multiple Event Transient analysis

Quantitative evaluation of soft error injection techniques for robust system design

Efficiently tolerating timing violations in pipelined microprocessors

Hierarchical decoding of double error correcting codes for high speed reliable memories

Power benefit study for ultra-high density transistor-level monolithic 3D ICs

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations

Minimum-energy state guided physical design for Nanomagnet Logic

Ultra low power associative computing with spin neurons and resistive crossbar memory

Understanding the trade-offs in multi-level cell ReRAM memory design

Exploring Tunnel-FET for ultra low power analog applications: A case study on operational transconductance amplifier

Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints

Relax-and-Retime: A methodology for energy-efficient recovery based design

Post-placement voltage island generation for timing-speculative circuits

Analysis and characterization of inherent application resilience for approximate computing

Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Energy optimization by exploiting execution slacks in streaming applications on Multiprocessor Systems

Verifying SystemC using an intermediate verification language and symbolic simulation

Handling design and implementation optimizations in equivalence checking for behavioral synthesis

A counterexample-guided interpolant generation algorithm for SAT-based model checking

A robust constraint solving framework for multiple constraint sets in Constrained Random Verification

Simulation knowledge extraction and reuse in constrained random processor verification

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation

The role of Cascade, a cycle-based simulation infrastructure, in designing the Anton special-purpose supercomputers

Towards structured ASICs using polarity-tunable Si nanowire transistors

Sacha: The stanford carbon nanotube controlled handshaking robot

Electrical artificial skin using ultraflexible organic transistor

Relays do not leak - CMOS does

Single-photon image sensors

Non-volatile FPGAs based on spintronic devices

A novel analytical method for worst case response time estimation of distributed embedded systems

Optimizations for configuring and mapping software pipelines in many core systems

A scenario-based run-time task mapping algorithm for MPSoCs

Early exploration for platform architecture instantiation with multi-mode application partitioning

CoARX: A coprocessor for ARX-based cryptographic algorithms

Reconfigurable pipelined coprocessor for multi-mode communication transmission

Accelerators for biologically-inspired attention and recognition

Stochastic circuits for real-time image-processing applications

An event-driven simulation methodology for integrated switching power supplies in SystemVerilog

A new time-stepping method for circuit simulation

Time-domain segmentation based massively parallel simulation for ADCs

A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectrics

FPGA code accelerators - The compiler perspective

Can CAD cure cancer?

Let's put the car in your phone!

The undetectable and unprovable hardware Trojan horse

Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5Watts of power

Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching

Integrated instruction cache analysis and locking in multitasking real-time systems

Precise timing analysis for direct-mapped caches

SSDM: Smart Stack Data Management for software managed multicores (SMMs)

Taming the complexity of coordinated place and route

Routability-driven placement for hierarchical mixed-size circuit designs

Ripple 2.0: High quality routability-driven placement via global router integration

Optimization of placement solutions for routability

Exploration with upgradeable models using statistical methods for physical model emulation

Modular system-level architecture for concurrent cell balancing

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

DMR3D: Dynamic Memory Relocation in 3D Multicore Systems

Power gating applied to MP-SoCs for standby-mode power management

Power management and delivery for high-performance microprocessors

Flexible on-chip power delivery for energy efficient heterogeneous systems

Power and signal integrity challenges in 3D systems

Underpowering NAND flash: Profits and perils

New ERA: New efficient reliability-aware wear leveling for endurance enhancement of flash storage devices

SAW: System-assisted wear leveling on the write endurance of NAND flash devices

Performance enhancement of garbage collection for flash storage devices: An efficient victim block selection design

DuraCache: A durable SSD cache using MLC NAND flash

Distributed stable states for process networks - Algorithm, analysis, and experiments on intel SCC

Distributed run-time resource management for malleable applications on many-core platforms

netShip: A networked virtual platform for large-scale heterogeneous distributed embedded systems

Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems

On robust task-accurate performance estimation

Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors

HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors

Hierarchical power management for asymmetric multi-core in dark silicon era

Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor

Techniques for energy-efficient power budgeting in data centers

Temperature aware thread block scheduling in GPGPUs

VAWOM: Temperature and process variation aware WearOut Management in 3D multicore architecture

On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

An accurate semi-analytical framework for full-chip TSV-induced stress modeling

Speeding up computation of the max/min of a set of Gaussians for statistical timing analysis and optimization

InTimeFix: A low-cost and scalable technique for in-situ timing error masking in logic circuits

Improving PUF security with regression-based distiller

On the convergence of mainstream and mission-critical markets

DAC Design Automation Conference 2012

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

Design Automation Conference

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2007 44th ACM/IEEE Design Automation Conference

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Proceedings. 42nd Design Automation Conference, 2005.

Proceedings. 41st Design Automation Conference, 2004.

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)

Proceedings 37th Design Automation Conference

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

Proceedings of the 34th Design Automation Conference

33rd Design Automation Conference Proceedings, 1996

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[1992] Proceedings 29th ACM/IEEE Design Automation Conference

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