NDLI: Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures

Content Provider	IEEE Xplore Digital Library
Author	Roy, S. Choudhury, M. Puri, R. Pan, D.Z.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA (Roy, S.; Pan, D.Z.) \|\| IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA (Choudhury, M.; Puri, R.)
Abstract	This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like bit-wise output logic level. Besides having the best performance-area trade-off our approach, unlike existing techniques, can (i) handle more complex constraints such as maximum node fanout or wirelength that impact the performance/area of a design and (ii) generate several feasible solutions that minimize the objective function. Generating several optimal solutions provides the option to choose adder designs that mitigate constraints such as wire congestion or power consumption that are difficult to model as constraints during logic synthesis. Experimental results demonstrate that our approach improves performance by 3% and area by 9% over even a 64-bit full custom designed adder implemented in an industrial high-performance design.
Starting Page	1
Ending Page	8
File Size	246580
Page Count	8
File Format	PDF
ISBN	9781450320719
ISSN	0738100X
DOI	10.1145/2463209.2488793
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Adders Indexes Data structures Algorithm design and analysis Dynamic programming Heuristic algorithms Runtime Bottom-up approach Logic synthesis Parallel prefix adder
Content Type	Text
Resource Type	Article

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Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures

Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures

Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures.

Non-Heuristic Optimization and Synthesis of Parallel-Prefix Adders (1996)

Area minimization algorithm for parallel prefix adders under bitwise delay constraints

Area-Time Optimal Adder Design

Optimized design of parallel prefix Ling adder

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A new approach to implement parallel prefix adders in an.

Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures

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