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Content Provider | IEEE Xplore Digital Library |
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Author | Bo-Han Wu Chung-Yang Huang |
Copyright Year | 2013 |
Description | Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Bo-Han Wu; Chung-Yang Huang) |
Abstract | To verify system-wide properties on SoC designs in Constrained Random Verification (CRV), the default set of constraints to generate patterns could be overridden frequently through the complex testbench. It usually results in the degradation of pattern generation speed because of low hit-rate problems. In this paper, we propose a technique to preprocess the solution space under each constraint set. Regarding the similarity between constraint sets, the infeasible subspaces under a constraint set help identify the infeasible subspaces under another constraint set. The profiled results under each constraint set are then stored in a distinct range-splitting tree (RS-Tree). These trees accelerate pattern generation under multiple constraint sets and, simultaneously, ensure the produced patterns are evenly-distributed. In our experiments, our framework achieved 10X faster pattern generation speed than a state-of-art tool in average. |
Starting Page | 1 |
Ending Page | 7 |
File Size | 769412 |
Page Count | 7 |
File Format | |
ISBN | 9781450320719 |
ISSN | 0738100X |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2013-05-29 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Association for Computing Machinery, Inc. (ACM) |
Subject Keyword | Runtime Estimation Acceleration Legged locomotion Inference algorithms System-on-chip Degradation Constrained Random Verification (CRV) Functional Verification |
Content Type | Text |
Resource Type | Article |
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