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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jie Zhang Feng Yuan Lingxiao Wei Zelong Sun Qiang Xu |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China (Jie Zhang; Feng Yuan; Lingxiao Wei; Zelong Sun; Qiang Xu) |
| Abstract | Hardware Trojans (HTs) implemented by adversaries serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or Denial of Service attacks. To tackle such threats, this paper proposes a novel verification technique for hardware trust, namely VeriTrust, which facilitates to detect HTs inserted at design stage. Based on the observation that HTs are usually activated by dedicated trigger inputs that are not sensitized with verification test cases, VeriTrust automatically identifies such potential HT trigger inputs by examining verification corners. The key difference between VeriTrust and existing HT detection techniques is that VeriTrust is insensitive to the implementation style of HTs. Experimental results show that VeriTrust is able to detect all HTs evaluated in this paper (constructed based on various HT design methodologies shown in the literature) at the cost of moderate extra verification time, which is not possible with existing solutions. |
| Starting Page | 1 |
| Ending Page | 8 |
| File Size | 435989 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781450320719 |
| ISSN | 0738100X |
| DOI | 10.1145/2463209.2488808 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Hardware Measurement Detection algorithms Integrated circuit modeling Payloads Runtime |
| Content Type | Text |
| Resource Type | Article |
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