NDLI: Automatic stability checking for large linear analog integrated circuits

Content Provider	IEEE Xplore Digital Library
Author	Mukherjee, P. Fang, G.P. Burt, R. Peng Li
Copyright Year	2011
Description	Author affiliation: Department of Electrical and Computer Engineering, Texas A&M University, USA (Mukherjee, P.; Peng Li) \|\| Texas Instruments Inc., USA (Fang, G.P.; Burt, R.)
Abstract	Stability analysis is one of the key challenges in the design of large linear analog circuits with complex multi-loop structures. In this paper, we present an efficient loop finder algorithm to identify potentially unstable loops in such circuits. At the heart of our automated stability checker lie two newly developed computationally efficient algorithms — the first to detect all poles within a given region of interest and the second to extract second order approximations of node impedance transfer functions given these pole locations. It is shown that the proposed technique outperforms existing stability methods by more than one order of magnitude for medium sized circuits and enables stability analysis of large extracted industrial designs which was previously infeasible.
Starting Page	304
Ending Page	309
File Size	198981
Page Count	6
File Format	PDF
ISBN	9781450306362
ISSN	85644924
e-ISBN	9781450306362
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Partitioning algorithms Algorithm design and analysis Eigenvalues and eigenfunctions Approximation algorithms Stability analysis Impedance Mathematical model Model order reduction Small-signal analysis Analog circuit design Eigenvalue problem
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Automatic stability checking for large linear analog integrated circuits

Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits

Computational method of stability investigation for large analog circuits

PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits

A method for partitioning large graphs

Passivity-Preserving Model Reduction Using Dominant Spectral-Zero Interpolation

Model order reduction by a projection technique implemented on state equations

Small-Signal Stability Analysis of Microgrid Based on Perturbation Theory

An efficient test vector generation for checking analog/mixed-signal functional models

Automatic stability checking for large linear analog integrated circuits

Similar Documents

Automatic stability checking for large linear analog integrated circuits

Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits

Computational method of stability investigation for large analog circuits

PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits

A method for partitioning large graphs

Passivity-Preserving Model Reduction Using Dominant Spectral-Zero Interpolation

Model order reduction by a projection technique implemented on state equations

Small-Signal Stability Analysis of Microgrid Based on Perturbation Theory

An efficient test vector generation for checking analog/mixed-signal functional models

Automatic stability checking for large linear analog integrated circuits