NDLI: Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache

Content Provider	IEEE Xplore Digital Library
Author	Young Geun Choi Sungjoo Yoo Sunggu Lee Jung Ho Ahn
Copyright Year	2011
Description	Author affiliation: Graduate School of Convergence Science and Technology, Seoul National University, Korea (Jung Ho Ahn) \|\| Department of Electronic and Electrical Engineering, POSTECH, Korea (Young Geun Choi; Sungjoo Yoo; Sunggu Lee)
Abstract	Cache is a roadblock towards low supply voltage (Vcc). It is mainly because low Vcc incurs process variation-induced bit errors in large SRAM in cache. Existing approaches for low Vcc cache suffer from low performance due to reduced effective capacity, long latency to correct errors, and increased misses due to accesses to faulty words. In our work, we propose a word-level sub-block disable-based method which increases the utilization of available cache capacity. Our key idea is to minimize accesses to faulty words. To do that, we propose utilizing access behavior history in allocating cache resource with faulty words. In addition, we propose remapping cache words inside of cache line in order to better match both access and error patterns. Experimental results show that the proposed method gives average 21.8% (up to 34.0%) performance improvement with a small area overhead in L1 and L2 caches.
Starting Page	978
Ending Page	983
File Size	347508
Page Count	6
File Format	PDF
ISBN	9781450306362
ISSN	85644924
e-ISBN	9781450306362
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Random access memory Pattern matching Error correction Error correction codes Error analysis Art Sensitivity analysis access pattern Cache Vccmin bit error
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache

MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache

Low Vccmin fault-tolerant cache with highly predictable performance

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

Single b-bit byte error correcting and double bit error detecting codes for high-speed memory systems

A Framework for the Correction of Multi-Bit Errors in Multi-Core Processors

Stepped parity: A low-cost multiple bit upset detection technique

Architectural-level error-tolerant techniques for low supply voltage cache operation

Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache

Similar Documents

Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache

MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache

Low Vccmin fault-tolerant cache with highly predictable performance

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

Single b-bit byte error correcting and double bit error detecting codes for high-speed memory systems

A Framework for the Correction of Multi-Bit Errors in Multi-Core Processors

Stepped parity: A low-cost multiple bit upset detection technique

Architectural-level error-tolerant techniques for low supply voltage cache operation

Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache