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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhiwei Qin Yi Wang Duo Liu Zili Shao Yong Guan |
| Copyright Year | 2011 |
| Description | Author affiliation: Dept. of Computing, The Hong Kong Polytechnic Univ., Hung Hom, Hong Kong (Zhiwei Qin; Yi Wang; Duo Liu; Zili Shao) || College of Comp. & Info. Mgmt., Captial Normal Univ., Beijing, China (Yong Guan) |
| Abstract | The new write constraints of multi-level cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work. |
| Starting Page | 17 |
| Ending Page | 22 |
| File Size | 317810 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781450306362 |
| ISSN | 85644924 |
| e-ISBN | 9781450306362 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-06-05 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Ash Random access memory Time factors Memory management Benchmark testing Flash memory System performance Garbage collection MLC NAND flash memory Flash translation layer Address mapping |
| Content Type | Text |
| Resource Type | Article |
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