NDLI: Panel: Deep Submicron Design Challenges

Content Provider	IEEE Xplore Digital Library
Author	Mike Smith
Copyright Year	1995
Description	Author affiliation: Compass Design Automation, San Jose, CA (Mike Smith)
Abstract	This panel will provide access to a group of ASIC engineers familiar with the problems of deep submicron design that will face us in the near future. As we move to deep submicron CMOS processes we are scaling the metal linewidth but not the thickness. This is increasing the parasitic capacitance of the wires to the point where the typical interconnect delay is larger than a gate delay. At the moment synthesis tools work by minimizing the number of literals in Boolean logic expressions and mapping to gates in a cell library with the smallest databook delay values. Instead of concentrating on logic synthesis and pre-layout simulation and adding the wires, almost as an afterthought, we will need to think far more carefully about interconnect. One of the ways to do this is to couple the synthesis and physical layout steps far more tightly than they are now. It is not at all clear how best to do this. Interconnect is one of the biggest, most visible, and perhaps most easily understood problems in deep submicron design, but there are others. In fact, there are many second- and third-order physical effects that are starting to become more important. In the past we have swept these problems under the carpet by using worst-case design. We can no longer afford the increasing number and increasing size of these pessimistic assumptions. Some other examples of effects we will need to consider: We will have to pay more attention to the shape of logic waveforms and not just their delay. Many ASIC vendors have already started to account for the effect of rise and fall times. We will need to develop methods to tackle interconnect coupling. We cannot afford to extract all coupling capacitances. With deep submicron processes we are moving into an era where we need low-power design, since batteries and packages donÕt seem to be keeping up. We need new tools and methods to help us in this area. Lithography is becoming very difficult as we run out of room in the light spectrum. At the moment we put what we want on a mask and expect the lithography engineers to reproduce it on silicon. This may not continue to be possible.
Starting Page	673
Ending Page	673
File Size	9374
Page Count	1
File Format	PDF
ISBN	0897917251
ISSN	0738100X
DOI	10.1109/DAC.1995.250049
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-06-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Delay Application specific integrated circuits Wires Lithography Design engineering CMOS process Parasitic capacitance CMOS logic circuits Boolean functions Libraries
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Self-timed logic using current-sensing completion detection (CSCD)

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

CubicWare: a hierarchical design system for deep submicron ASIC

Logical-physical co-design for deep submicron circuits: challenges and solutions

An ECL logic synthesis system

Boolean Function Matching using Walsh Spectral Decision Diagrams

Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered

Pre-layout delay calculation specification for CMOS ASIC libraries

Processor chip design on submicron ASICs

Panel: Deep Submicron Design Challenges

Similar Documents

Self-timed logic using current-sensing completion detection (CSCD)

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

CubicWare: a hierarchical design system for deep submicron ASIC

Logical-physical co-design for deep submicron circuits: challenges and solutions

An ECL logic synthesis system

Boolean Function Matching using Walsh Spectral Decision Diagrams

Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered

Pre-layout delay calculation specification for CMOS ASIC libraries

Processor chip design on submicron ASICs

Panel: Deep Submicron Design Challenges