NDLI: Accurate Estimation of Combinational Circuit Activity

Content Provider	IEEE Xplore Digital Library
Author	Mehta, Huzefa Borah, Manjit Owens, Robert Michael Irwin, Mary Jane
Copyright Year	1995
Description	Author affiliation: Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA (Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin)
Abstract	Several techniques to estimate power consumption of a combinational circuit using probabilistic methods have been proposed. However none of these techniques take into account circuit activity when two or more inputs change simultaneously or when glitching occurs. A formulation is presented in this paper which includes signal correlation and multiple gate input switching. Work is also presented in estimating the glitching contribution to the switching activity. Results obtained from benchmarks and test circuits show very good accuracy when compared to actual activities as measured by SPICE and IRSIM.
Starting Page	618
Ending Page	622
File Size	214513
Page Count	5
File Format	PDF
ISBN	0897917251
ISSN	0738100X
DOI	10.1109/DAC.1995.250039
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-06-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Combinational circuits Switching circuits Power dissipation Delay estimation Circuit simulation Circuit testing Semiconductor device modeling Computer science Power engineering and energy State estimation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Runtime leakage power estimation technique for combinational circuits

Power estimation considering statistical IC parametric variations

An efficient method for estimating switching activity in arithmetic circuits using a lumped delay model

A Cell-based Power Estimation In Cmos Combinational Circuits

Power-delay characteristics of CMOS multipliers

A non-zero delay model for glitch analysis in logic circuits

Estimation of power dissipation in CMOS combinational circuits

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

Accurate Estimation of Combinational Circuit Activity

Similar Documents

Runtime leakage power estimation technique for combinational circuits

Power estimation considering statistical IC parametric variations

An efficient method for estimating switching activity in arithmetic circuits using a lumped delay model

A Cell-based Power Estimation In Cmos Combinational Circuits

Power-delay characteristics of CMOS multipliers

A non-zero delay model for glitch analysis in logic circuits

Estimation of power dissipation in CMOS combinational circuits

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

Accurate Estimation of Combinational Circuit Activity