NDLI: An Algorithm for Incremental Timing Analysis

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DAC '95 Cover page

DAC'95 Title Page

DAC'95 Copyright Page

Executive Committee

General Chair's Welcome

Technical Program Committee

Call for Papers

Design Automation Conference Scholarship Awards

1995 Keynote Address

Table of contents

Panel: Executive Perspective on the Future of the EDA Industry and Design Technology

A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC™ -I

System Design Methodology of UltraSPARC™ -I

UltraSPARC™ -I Emulation

CAD Methodology for the Design of UltraSPARC™ -I Microprocessor at Sun Microsystems Inc.

Computing the Maximum Power Cycles of a Sequential Circuit

Register Allocation and Binding for Low Power

Memory Segmentation to Exploit Sleep Mode Operation

Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level

Boolean Matching for Incompletely Specified Functions

Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm

A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis

Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping

Minimizing the Routing Cost During Logic Extraction

Requirements-Based Design Evaluation

Incorporating Design Schedule Management into a Flow Management System

Generating ECAD Framework Code from Abstract Models

Tool Integration and Construction Using Generated Graph-Based Design Representations

Panel: Managing Design Change - Lessons Learned

Scheduling Using Behavioral Templates

Rephasing: A Transformation Technique for the Manipulation of Timing Constraints

Optimal ILP-based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming

Fast Identification of Robust Dependent Path Delay Faults

On Synthesis-for-Testability of Combinational Logic Circuits

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits using Compact Lists

Parallel Logic Simulation of VLSI Systems

Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors

A General Method for Compiling Event-Driven Simulations

Panel: Power Minimization in IC Design

A Transformation-Based Approach for Storage Optimization

Register Minimization beyond Sharing among Variables

Constrained Register Allocation in Bus Architectures

On Test Set Preservation of Retimed Circuits

Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation

Partial Scan with Pre-selected Scan Signals

Spectral Partitioning: The More Eigenvectors, The Better

Multi-way Partitioning For Minimum Delay For Look-Up Table Based FPGAs

Performance-Driven Partitioning Using a Replication Graph Approach

Timing Driven Placement for Large Standard Cell Circuits

Quantified Suboptimality of VLSI Layout Heuristics

Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System Simulation

Digital Receiver Design Using VHDL Generation From Data Flow Graphs

Logic Verification Methodology for PowerPC™ Microprocessors

Panel: University-Industry Ties: How Can They Be Improved?

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits

Logic Extraction and Factorization for Low Power

Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool

The Aurora RAM Compiler

Automatic Layout Synthesis of Leaf Cells

Delayed Frontal Solution for Finite-Element based Resistance Extraction

Test Program Generation for Functional Verification of PowePC Processors in IBM

Behavioral Synthesis Methodology for HDL-Based Specification and Validation

Design-Flow and Synthesis for ASICs: A Case Study

Model Checking in Industrial Hardware Design

DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling

A Fresh Look at Retiming via Clock Skew Optimization

The Validity of Retiming Sequential Circuits

Retiming Synchronous Circuitry with Imprecise Delays

A Fast State Assignment Procedure for Large FSMs

Software Accelerated Functional Fault Simulation for Data-Path Architectures

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy

Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks

Analysis of Switch-Level Faults by Symbolic Simulation

Transmission Line Synthesis

The Elmore Delay as a Bound for RC Trees with Generalized Input Signals

Delay Analysis of the Distributed RC Line

Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances associated with 3-D Interconnect Structures

Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs

Tutorial: ASIC Prototyping

Symbolic Modeling and Evaluation of Data Paths

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead

Deriving Efficient Area and Delay Estimates by Modeling Layout Tools

Efficient OBDD-Based Boolean Manipulation in CAD Beyond Current Limits

Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment

Advanced Verification Techniques Based on Learning

Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking

DARWIN: CMOS opamp Synthesis by Means of a Genetic Algorithm

Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels

Direct Performance-Driven Placement of Mismatch-sensitive Analog Circuits

System-Level Design for Test of Fully Differential Analog Circuits

Panel: DOS, Windows, UNIX: EDA and the OS Wars

Performance Analysis of Embedded Software Using Implicit Path Enumeration

Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems

Interfacing Incompatible Protocols Using Interface Process Generation

Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm

Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods

Transient Simulations of Three-dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume approach

Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution

Power Optimal Buffered Clock Tree Design

Power Distribution Topology Design

On the Bounded-Skew Clock and Steiner Routing Problems

Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems

A Methodology for HW-SW Codesign in ATM

Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation

Panel: The ESDA Landscape: Who Will Dominate?

Verification of Arithmetic Circuits with Binary Moment Diagrams

Residue BDD and Its Application to the Verification of Arithmetic Circuits

Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions

On Optimal Board-Level Routing for FPGA-based Logic Emulation

A Performance and Routability Driven Router for FPGAs Considering Path Delays

New Performance-Driven FPGA Routing Algorithms

Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing

Effects of FPGA Architecture on FPGA Routing

The Case for Design Using the World Wide Web

Panel: The Impact of the World Wide Web on Electronic Design and EDA

Synthesis of Software Programs for Embedded Control Applications

Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores

Code Optimization Techniques for Embedded DSP Microprocessors

Retargetable Self-Test Program Generation Using Constraint Logic Programming

Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits

Accurate Estimation of Combinational Circuit Activity

Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuitsy

Efficient Power Estimation for Highly Correlated Input Streams

Power Estimation in Sequential Circuitsy

New Ideas for Solving Covering Problems

Logic Synthesis for Engineering Change

A Partitioning-based Logic Optimization Method for Large Scale Circuits with Boolean Matrix

Multi-Level Logic Minimization based on Multi-Signal Implications

An Efficient Algorithm for Local Don't Care Sets Calculation

Logic Clause Analysis for Delay Optimization

Panel: Deep Submicron Design Challenges

Productivity Issues in High-Level Design: Are Tools Solving the Real Problems?

Information Models of VHDL

Measures of Syntactic Complexity for Modeling Behavioral VHDL

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization

An Algorithm for Incremental Timing Analysis

An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard cells

Automatic Clock Abstraction from Sequential Circuits

Hierarchical Optimization of Asynchronous Circuits

Externally Hazard-Free Implementations of Asynchronous Circuits

A Design and Validation System for Asynchronous Circuits

Conference Author / Panelist Index

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An Algorithm for Incremental Timing Analysis

Content Provider	IEEE Xplore Digital Library
Author	Jin-fuw Lee, Donald T. Tang
Copyright Year	1995
Description	Author affiliation: IBM Thomas J. Watson Research Center, Yorktown Heights, NY (Jin-fuw Lee, Donald T. Tang)
Abstract	In recent years, many new algorithms have been proposed for performing a complete timing analysis of sequential logic circuits. In this paper, we present an incremental timing analysis algorithm. When an incremental design change is made on the logic network, this algorithm will identify the portion of design for which the timing is affected, and quickly derive the new arrival times and slacks. A fast incremental timing analysis is desirable for users doing interactive logic design. It is particularly important for a logic synthesis program, which needs to evaluate the circuit delays under many logic modifications.
Starting Page	696
Ending Page	701
File Size	135399
Page Count	6
File Format	PDF
ISBN	0897917251
ISSN	0738100X
DOI	10.1109/DAC.1995.250054
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-06-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Timing Algorithm design and analysis Latches Clocks Sequential circuits Logic design Delay Performance analysis Logic circuits Pattern analysis
Content Type	Text
Resource Type	Article

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