NDLI: Pre-layout delay calculation specification for CMOS ASIC libraries

Content Provider	IEEE Xplore Digital Library
Author	Edamatsu, H. Homma, K. Kakimoto, M. Koike, Y. Tabuchi, K.
Copyright Year	1998
Description	Author affiliation: Corp. Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan (Edamatsu, H.)
Abstract	This paper describes the delay calculation method and the accuracy analysis of its interpolation for CMOS ASIC libraries which contain cell-based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification, and logic synthesis. The delay calculation method addressed in this paper is specified as IEC CDV 61523-2 standard which consists of the estimation of wire capacitance, and the delay calculation method based on a table look-up. Although the input to the delay calculator is net list and library parameters, the delay parameter part of the library has not been standardized because of its strong dependency on the delay calculation method. We, IEC/TC93/WG2/ALR group, specified it based on the EIAJ work. In IEC CDV 61523-2, we specified in detail a table look up calculation formula for CMOS ASIC library using a linear interpolation in the triangular area which is more accurate than the bilinear interpolation. In this paper, we overview the specification and provide the mathematical background for the interpolation.
Starting Page	241
Ending Page	248
File Size	634180
Page Count	8
File Format	PDF
ISBN	0780344251
DOI	10.1109/ASPDAC.1998.669457
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-02-13
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Libraries Interpolation Delay estimation IEC standards CMOS logic circuits Logic design Analytical models Timing Added delay
Content Type	Text
Resource Type	Article

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