NDLI: A buffer planning algorithm based on dead space redistribution

Content Provider	IEEE Xplore Digital Library
Author	Song Chen Xianlong Hong Sheqin Dong Yuchun Ma Yici Cai Chung-Kuan Cheng Jun Gu
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Song Chen; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai)
Abstract	This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by freely moving some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by experimental results. The increment of the number of nets that satisfy delay constraints is 9% on an average.
Sponsorship	IEEE Circuits & Syst. Soc. ACM SIGDA IEICE (Inst. Electon., Inf. & Commun. Eng.) IPSJ (Inf. Process. Soc. Japan)
Starting Page	435
Ending Page	438
File Size	526188
Page Count	4
File Format	PDF
ISBN	0780376595
DOI	10.1109/ASPDAC.2003.1195055
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Space technology Delay Integrated circuit interconnections Computer science Wire Timing Technology planning Circuit topology Very large scale integration Frequency
Content Type	Text
Resource Type	Article

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