NDLI: Highly scalable algorithms for rectilinear and octilinear Steiner trees

Content Provider	IEEE Xplore Digital Library
Author	Kahng, A.B. Mandoiu, I.I. Zelikovsky, A.Z.
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, CA, USA (Kahng, A.B.; Mandoiu, I.I.)
Abstract	The rectilinear Steiner minimum tree (RSMT) problem, which asks for a minimum-length interconnection of a given set of terminals in the rectilinear plane, is one of the fundamental problems in electronic design automation. Recently there has been renewed interest in this problem due to the need for highly scalable algorithms able to handle nets with tens of thousands of terminals. In this paper we give a practical O(n log/sup 2/ n) heuristic for computing near-optimal rectilinear Steiner trees based on a hatched version of the greedy triple contraction algorithm of Zelikovsky (Algorithmica vol. 9, pp. 463-470, 1993). Experiments conducted on both random and industry test cases show that our heuristic matches or exceeds the quality of best known RSMT heuristics, e.g. on random instances with more than 100 terminals our heuristic improves over the rectilinear minimum spanning tree by an average of 11%. Moreover, our heuristic has very good runtime scaling, e.g. it can route a 34k-terminals net extracted from a real design in less than 25 seconds compared to over 86 minutes needed by the O(n/sup 2/) edge-based heuristic of Borah, Owens, and Irwin (Discrete Appl. Math. vol. 90, pp. 51-67, 1999). Since our heuristic is graph-based, it can be easily modified to handle practical considerations such as routing obstacles, preferred directions, via costs, and octilinear routing - indeed, experimental results show only a small factor increase in runtime when switching from rectilinear to octilinear routing.
Sponsorship	IEEE Circuits & Syst. Soc. ACM SIGDA IEICE (Inst. Electon., Inf. & Commun. Eng.) IPSJ (Inf. Process. Soc. Japan)
Starting Page	827
Ending Page	833
File Size	680217
Page Count	7
File Format	PDF
ISBN	0780376595
DOI	10.1109/ASPDAC.2003.1195132
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Runtime Steiner trees Electronic design automation and methodology Testing Computer science Costs Tree graphs Silicon Research and development
Content Type	Text
Resource Type	Article

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