NDLI: Fast buffer planning and congestion optimization in interconnect-driven floorplanning

Content Provider	IEEE Xplore Digital Library
Author	Wong, K.W.C. Young, E.F.Y.
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China (Wong, K.W.C.; Young, E.F.Y.)
Abstract	In this paper, we study and implement a routability-driven floorplanner with congestion estimation and buffer block planning. We assume that buffers should be inserted at flexible intervals from each other for long enough wires. Under this buffer insertion constraint, our floorplanner estimates congestion by computing the best possible buffer locations for each net and performs probabilistic analysis based on the solution. Dynamic programming is used such that estimations can be done very effectively. Nets are topologically grouped to consider bus-based routing and to facilitate the estimation process. We compare our results with those in paper (C. W. Sham et al, Proc. Int. Symp. on Physical Design, pp. 50-55, 2002) which are the latest results for this problem, and show that our approach can perform better in both quality and runtime.
Sponsorship	IEEE Circuits & Syst. Soc. ACM SIGDA IEICE (Inst. Electon., Inf. & Commun. Eng.) IPSJ (Inf. Process. Soc. Japan)
Starting Page	411
Ending Page	416
File Size	623501
Page Count	6
File Format	PDF
ISBN	0780376595
DOI	10.1109/ASPDAC.2003.1195050
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Routing Dynamic programming Wires Delay Timing Computer science Performance analysis Runtime Very large scale integration
Content Type	Text
Resource Type	Article

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